External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Write Data Valid Window and Eye Diagram

The FPGA generates the write signals. Take measurements at the memory device end of the line.

To ease write diagram capture, modify the example driver to mask reads or modify the PHY export a signal that is asserted when performing writes.