Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents

2.6. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History

Document Version Intel® Quartus® Prime Version Changes
2024.02.21 18.1.0
  • Clarified constraint precedence in Maximum Skew and Timing Constraint Precedence topics.
2018.09.24 18.1.0
  • Revised "Basic Timing Analysis Flow" section to add sequential step organization, update steps, and add supporting screenshots.
  • Retitled "SDC Constraint Creation Summary" to " Dual Clock SDC Example."
  • Retitled "Default Settings" to "Default Multicycle Analysis."
  • Retitled "SDC (Clock and Exception) Assignments on Blackbox Ports" to "Constraining Design Partition Ports."
2015.11.02 15.1.0
  • Changed instances of Quartus II to Quartus Prime.
  • Updated information on using Intel® Arria® 10 devices with enhanced timing algorithms.
2015.05.04 15.0.0 Added and updated contents in support of new timing algorithms for Arria 10:
  • Enhanced Timing Analysis for Arria 10
  • Maximum Skew (set_max_skew command)
  • Net Delay (set_net_delay command)
  • Create Generated Clocks (clock-as-data example)
2014.12.15 14.1.0 Major reorganization. Revised and added content to the following topic areas:
  • Timing Constraints
  • Create Clocks and Clock Constraints
  • Creating Generated Clocks
  • Creating Clock Groups
  • Clock Uncertainty
  • Running the Timing Analyzer
  • Generating Timing Reports
  • Understanding Results
  • Constraining and Analyzing with Tcl Commands
August 2014 14.0a10.0 Added command line compilation requirements for Arria 10 devices.
June 2014 14.0.0
  • Minor updates.
  • Updated format.
November 2013 13.1.0
  • Removed HardCopy device information.
June 2012 12.0.0
  • Reorganized chapter.
  • Added “Creating a Constraint File from Intel® Quartus® Prime Templates with the Intel® Quartus® Prime Text Editor” section on creating an SDC constraints file with the Insert Template dialog box.
  • Added “Identifying the Intel® Quartus® Prime Software Executable from the SDC File” section.
  • Revised multicycle exceptions section.
November 2011 11.1.0
  • Consolidated content from the Best Practices for the Intel® Quartus® Prime Timing Analyzer chapter.
  • Changed to new document template.
May 2011 11.0.0
  • Updated to improve flow. Minor editorial updates.
December 2010 10.1.0
  • Changed to new document template.
  • Revised and reorganized entire chapter.
  • Linked to Intel® Quartus® Prime Help.
July 2010 10.0.0 Updated to link to content on SDC commands and the Timing Analyzer GUI in Intel® Quartus® Prime Help.
November 2009 9.1.0 Updated for the Intel® Quartus® Prime software version 9.1, including:
  • Added information about commands for adding and removing items from collections
  • Added information about the set_timing_derate and report_skew commands
  • Added information about worst-case timing reporting
  • Minor editorial updates
November 2008 8.1.0 Updated for the Intel® Quartus® Prime software version 8.1, including:
  • Added the following sections:

    “set_net_delay” on page 7–42

    “Annotated Delay” on page 7–49

    “report_net_delay” on page 7–66

  • Updated the descriptions of the -append and -file < name > options in tables throughout the chapter
  • Updated entire chapter using 8½” × 11” chapter template
  • Minor editorial updates