ID 683068
Date 9/24/2018
Public

## 2.3.4.2. Creating Virtual Clocks

A virtual clock is a clock without a real source in the design, or a clock that does not interact directly with the design. You can use Virtual clocks in I/O constraints to represent the clock at the external device connected to the FPGA.

To create virtual clocks, use the create_clock constraint with no value for the <targets> option.

This following example defines a 100Mhz virtual clock because the command includes no <targets>.

create_clock -period 10 -name my_virt_clk

### I/O Constraints with Virtual Clocks

For the output circuit shown in the following figure, you can use a base clock to constrain the circuit in the FPGA, and a virtual clock to represent the clock driving the external device. The following figure shows the base clock (system_clk), virtual clock (virt_clk), and output delay for the Virtual Clock Constraints example below.

Figure 45. Virtual Clock Board Topology

The following creates the 10 ns virt_clk virtual clock, with a 50% duty cycle, with the first rising edge occurring at 0 ns. The virtual clock can then become the clock source for an output delay constraint.

### Virtual Clock Constraints

#create base clock for the design
create_clock -period 5 [get_ports system_clk]
#create the virtual clock for the external register
create_clock -period 10 -name virt_clk
#set the output delay referencing the virtual clock
set_output_delay -clock virt_clk -max 1.5 [get_ports dataout]
set_output_delay -clock virt_clk -min 0.0 [get_ports dataout]