Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer
ID
683068
Date
2/21/2024
Public
2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.4.1. Creating Base Clocks
2.3.4.2. Creating Virtual Clocks
I/O Constraints with Virtual Clocks
Virtual Clock Constraints
2.3.4.3. Creating Generated Clocks (create_generated_clock)
2.3.4.4. Deriving PLL Clocks
2.3.4.5. Creating Clock Groups (set_clock_groups)
2.3.4.6. Accounting for Clock Effect Characteristics
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.3.4.2. Creating Virtual Clocks
A virtual clock is a clock without a real source in the design, or a clock that does not interact directly with the design. You can use Virtual clocks in I/O constraints to represent the clock at the external device connected to the FPGA.
To create virtual clocks, use the create_clock constraint with no value for the <targets> option.
This following example defines a 100Mhz virtual clock because the command includes no <targets>.
create_clock -period 10 -name my_virt_clk
I/O Constraints with Virtual Clocks
For the output circuit shown in the following figure, you can use a base clock to constrain the circuit in the FPGA, and a virtual clock to represent the clock driving the external device. The following figure shows the base clock (system_clk), virtual clock (virt_clk), and output delay for the Virtual Clock Constraints example below.
Figure 45. Virtual Clock Board Topology
The following creates the 10 ns virt_clk virtual clock, with a 50% duty cycle, with the first rising edge occurring at 0 ns. The virtual clock can then become the clock source for an output delay constraint.
Virtual Clock Constraints
#create base clock for the design create_clock -period 5 [get_ports system_clk] #create the virtual clock for the external register create_clock -period 10 -name virt_clk #set the output delay referencing the virtual clock set_output_delay -clock virt_clk -max 1.5 [get_ports dataout] set_output_delay -clock virt_clk -min 0.0 [get_ports dataout]