ID 683068
Date 9/24/2018
Public

## 2.3.6.3. Net Delay (set_net_delay)

Use the set_net_delay command to set the net delays and perform minimum or maximum timing analysis across nets.

The -from and -to options can be string patterns or pin, port, register, or net collections. When you use pin or net collection, include output pins or nets in the collection.

set_net_delay -from reg_a -to reg_c -max 20
Table 13.  set_net_delay Options
Arguments Description
-h | -help Short help.
-long_help Long help with examples and possible return values.
-from <names> Valid source pins, ports, registers or nets (Tcl matches string patterns).
-get_value_from_clock_period <src_clock_period|dst_clock_period|min_clock_period|max_clock_period> Option to interpret net delay constraint as a multiple of the clock period.
-max Specifies maximum delay.
-min Specifies minimum delay.
-to <names> 2 Valid destination pins, ports, registers or nets (Tcl matches string patterns).
-value_multiplier <multiplier> Value by which the clock period multiplies to compute net delay requirement.
<delay> Delay value.

If you use the -min option, the Timing Analyzer calculates slack by determining the minimum delay on the edge. If you use -max option, the Timing Analyzer calculates slack by determining the maximum edge delay.

Use -get_skew_value_from_clock_period to set the net delay requirement as a multiple of the launching or latching clock period, or whichever of the two has a smaller or larger period. If you use this option, you must also set -value_multiplier, and you must not set the positional delay option. If more than one clock clocks the set of nets, the Timing Analyzer uses the net with smallest period to compute the constraint for a -max constraint, and the largest period for a -min constraint. If there are no clocks clocking the endpoints of the net (that is, if the endpoints of the nets are not registers or constraint ports), then the Timing Analyzer ignores the net delay constraint.

2 If no -to option, or if -to is a wildcard ( "*") character, all the output pins and registers on timing netlist become valid destination points.

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