Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents Automatic Clock Detection and Constraint Creation

Use the derive_clocks command to automatically create base clocks in your design The derive_clocks command is equivalent to using the create_clock command for each register or port feeding the clock pin of a register. The derive_clocks command creates clock constraints on ports or registers to ensure every register in your design has a clock constraints, and it applies one period to all base clocks in your design.

The following command specifies a base clock with a 100 MHz requirement for unconstrained base clock nodes.

derive_clocks -period 10
Warning: Do not use the derive_clocks command for final timing sign-off; instead, you create clocks for all clock sources with the create_clock and create_generated_clock commands. If your design has more than a single clock, the derive_clocks command constrains all the clocks to the same specified frequency. To achieve a thorough and realistic analysis of your design’s timing requirements, make individual clock constraints for all clocks in your design.

If you want to create some base clocks automatically, use the -create_base_clocks option to derive_pll_clocks. With this option, the derive_pll_clocks command automatically creates base clocks for each PLL, based on the input frequency information that you specify when you generate the PLL. This feature works for simple port-to-PLL connections. Base clocks do not automatically generate for complex PLL connectivity, such as cascaded PLLs. You can also use the command derive_pll_clocks -create_base_clocks to create the input clocks for all PLL inputs automatically.