18.104.22.168.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
This example is a combination of the previous two examples. The destination clock frequency is an integer multiple of the source clock frequency, and the destination clock has a positive phase shift. The destination clock frequency is 5 ns, and the source clock frequency is 10 ns. The destination clock also has a positive offset of 2 ns with respect to the source clock. The destination clock frequency can be an integer multiple of the source clock frequency. The destination clock frequency can be with an offset when a PLL generates both clocks with a phase shift on the destination clock.
The following example shows a design in which the destination clock frequency is a multiple of the source clock frequency with an offset.
The timing diagram for the default setup check analysis the Timing Analyzer performs.
The setup relationship in this example demonstrates that the data does not require capture at edge one, but rather requires capture at edge two; therefore, you can relax the setup requirement. To adjust the default analysis, you shift the latch edge by one clock period, and specify an end multicycle setup exception of three.
The multicycle exception adjusts the default analysis in this example:
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \ -setup -end 3
The timing diagram for the preferred setup relationship for this example.
The following timing diagram shows the default hold check analysis that the Timing Analyzer performs with an end multicycle setup value of three:
In this example, the hold check one is too restrictive. The data is launched by the edge at 0 ns, and must check against the data that the previous latch edge at 2 ns captures. This event does not occur in hold check one. To adjust the default analysis, you assign end multicycle hold exception of one.
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