ID 683068
Date 9/24/2018
Public

## 2.1. Enhanced Timing Analysis for Intel® Arria® 10 Devices

The Timing Analyzer supports new timing algorithms for the Intel® Arria® 10 device family which significantly improve the speed of the analysis.

These algorithms are enabled by default for Intel® Arria® 10 devices, and can be enabled for earlier families with an assignment. The new analysis engine analyzes the timing graph a fixed number of times. Previous Timing Analyzer analysis analyzed the timing graph as many times as there were constraints in your Synopsys Design Constraint (SDC) file.

The new algorithms also support incremental timing analysis, which allows you to modify a single block and re-analyze while maintaining a fully analyzed design.

You can turn on the new timing algorithms for use with Arria® V, Cyclone® V, and Stratix® V devices with the following QSF assignment:
set_global_assignment -name TIMEQUEST2 ON

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