Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents Report Timing Command

The Report Timing command allows you to specify options for reporting the timing on any path or clock domain in the design.

To access Report Timing in the Timing Analyzer:

  • In the Tasks pane, click Reports > Custom Reports > Report Timing.
  • Right-click on nodes or assignments, and then click Report Timing.

You can specify the Clocks, Targets, Analysis Type, and Output options that you want to include in the report. For example, you can increase the number of paths to report, add a Target filter, add a From Clock, or write the report to a text file.

Figure 39. Report Timing Dialog Box
Table 6.  Report Timing Options
Option Description
Clocks From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify.
Targets Specifies the target node for From Clock and To Clock to report paths with only those endpoints. Specify an I/O or register name or I/O port for this option. The field also supports wildcard characters. For example, to report only paths within a specific hierarchy:
report_timing -from *|egress:egress_inst|* \
     -to *|egress:egress_inst|* -(other options)
When the From, To, or Through boxes are empty, the Timing Analyzer assumes all possible targets in the device. The Through option limits the report for paths that pass through combinatorial logic, or a particular pin on a cell.
Analysis type The Analysis type options are Setup, Hold, Recovery, or Removal.
Output The Detail level, allows you to specify the path types the analysis includes in output. Summary level includes basic summary reports. Path only displays all the detailed information, except the Data Path tab displays the clock tree as one line item. Review the Clock Skew column in the Summary report. If the skew is less than +/-150ps, the clock tree is well balanced between source and destination.

When higher clock skew is present, enable the Full path option. This option breaks the clock tree into greater detail, showing every cell, including the input buffer, PLL, global buffer (called CLKCTRL_), and any logic. Review this data to determine the cause of clock skew in your design. Use the Full path option for I/O analysis because only the source clock or destination clock is inside the FPGA, and therefore the delay is a critical factor to meet timing.

Enable multi corner reports Enables or disables multi-corner timing analysis. This option is on by default.
Report panel name Displays the name of the report panel. You can enable File name to write the information to a file. If you append .htm as a suffix, the Timing Analyzer produces the report as HTML.
Paths Specifies the number of paths to display by endpoint and slack level. The default value for Report number of paths is 10, otherwise, the report can be very long. Enable Pairs only to list only one path for each pair of source and destination. Limit further with Maximum number of paths per endpoints. You can also filter paths by entering a value in the Maximum slack limit field.
Tcl command Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file.