2.3.1. Recommended Initial SDC Constraints 2.3.2. SDC File Precedence 2.3.3. Iterative Constraint Modification 2.3.4. Creating Clocks and Clock Constraints 2.3.5. Creating I/O Constraints 2.3.6. Creating Delay and Skew Constraints 2.3.7. Creating Timing Exceptions 2.3.8. Example Circuit and SDC File
126.96.36.199.1. Default Multicycle Analysis 188.8.131.52.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 184.108.40.206.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 220.127.116.11.4. Same Frequency Clocks with Destination Clock Offset 18.104.22.168.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 22.214.171.124.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 126.96.36.199.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 188.8.131.52.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
184.108.40.206. Timing Paths
Timing paths connect two design nodes, such as the output of a register to the input of another register.
Understanding the types of timing paths is important to timing closure and optimization. The Timing Analyzer recognizes and analyzes the following timing paths:
- Edge paths—connections from ports-to-pins, from pins-to-pins, and from pins-to-ports.
- Clock paths—connections from device ports or internally generated clock pins to the clock pin of a register.
- Data paths—connections from a port or the data output pin of a sequential element to a port or the data input pin of another sequential element.
- Asynchronous paths—connections from a port or asynchronous pins of another sequential element such as an asynchronous reset or asynchronous clear.
Figure 3. Path Types Commonly Analyzed by the Timing Analyzer
In addition to identifying various paths in a design, the Timing Analyzer analyzes clock characteristics to compute the worst-case requirement between any two registers in a single register-to-register path. You must constrain all clocks in your design before analyzing clock characteristics.
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