Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents Timing Paths

Timing paths connect two design nodes, such as the output of a register to the input of another register.

Understanding the types of timing paths is important to timing closure and optimization. The Timing Analyzer recognizes and analyzes the following timing paths:

  • Edge paths—connections from ports-to-pins, from pins-to-pins, and from pins-to-ports.
  • Clock paths—connections from device ports or internally generated clock pins to the clock pin of a register.
  • Data paths—connections from a port or the data output pin of a sequential element to a port or the data input pin of another sequential element.
  • Asynchronous paths—connections from a port or asynchronous pins of another sequential element such as an asynchronous reset or asynchronous clear.
    Figure 3. Path Types Commonly Analyzed by the Timing Analyzer

In addition to identifying various paths in a design, the Timing Analyzer analyzes clock characteristics to compute the worst-case requirement between any two registers in a single register-to-register path. You must constrain all clocks in your design before analyzing clock characteristics.