ID 683068
Date 9/24/2018
Public

## 2.3.1.1. Create Clock (create_clock)

The Create Clock (create_clock) constraint allows you to define the properties and requirements for a clock in the design. You must define clock constraints to determine the performance of your design and constrain the external clocks coming into the FPGA. You can enter the constraints in the Timing Analyzer GUI, or in the .sdc file directly.

You specify the Clock name (-name), clock Period (-period), rising and falling Waveform edge values (-waveform), and the target signal(s) to which the constraints apply.

The following command creates the sys_clk clock with an 8ns period, and applies the clock to the fpga_clk port.:

create_clock -name sys_clk -period 8.0 \
[get_ports fpga_clk]

Note: Tcl and .sdc files are case-sensitive. Ensure that references to pins, ports, or nodes match the case of names in your design.

By default, the clock has a rising edge at time 0 ns, a 50% duty cycle, and a falling edge at time 4 ns. If you require a different duty cycle, or to represent an offset, specify the -waveform option.

Typically you name a clock with the same name as the port you assign. In the example above, the following constraint accomplishes this:

create_clock -name fpga_clk -period 8.0 [get_ports fpga_clk]

There are now two unique objects called fpga_clk, a port in your design and a clock applied to that port.

Note:

In Tcl syntax, square brackets execute the command inside them. [get_ports fpga_clk] executes a command that finds and returns a collection of all ports in the design that match fpga_clk. You can enter the command without using the get_ports collection command, as shown in the following example:

create_clock -name sys_clk -period 8.0 fpga_clk
Warning: Constraints that you define in the Timing Analyzer apply directly to the timing database, but do not automatically transfer to the .sdc file. Click Write SDC File on the Timing Analyzer Tasks pane to preserve constraints changes from the GUI in an .sdc file.