Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents Input Constraints (set_input_delay)

Input constraints allow specify all the external delays feeding the device. Specify input requirements for all input ports in your design.
set_input_delay -clock { clock } -clock_fall -fall -max 20 foo

Use the Set Input Delay (set_input_delay) constraint to specify external input delay requirements. Specify the Clock name (-clock) to reference the virtual or actual clock. You can specify a clock to allow the Timing Analyzer to correctly derive clock uncertainties for interclock and intraclock transfers. The clock defines the launching clock for the input port. The Timing Analyzer automatically determines the latching clock inside the device that captures the input data, because all clocks in the device are defined.

Figure 53. Input Delay Diagram
Figure 54. Input Delay Calculation