ID 683068
Date 9/24/2018
Public

## 2.3.1.2. Derive PLL Clocks (derive_pll_clocks)

The Derive PLL Clocks (derive_pll_clocks) constraint automatically creates clocks for each output of any PLL in your design.

The constraint can generate multiple clocks for each output clock pin if the PLL is using clock switchover: one clock for the inclk[0] input clock pin, and one clock for the inclk[1] input clock pin. Specify the Create base clocks (-create_base_clocks) option to create base clocks on the inputs of the PLLs by default. By default the clock name is the same as the output clock pin name, or specify the Use net name as clock name (-use_net_name) option to use the net name.

create_clock -period 10.0 -name fpga_sys_clk [get_ports fpga_sys_clk] \
derive_pll_clocks

When you create PLLs, you must define the configuration of each PLL output. This definition allows the Timing Analyzer to automatically constrain the PLLs with the derive_pll_clocks command. This command also constrains transceiver clocks and adds multicycles between LVDS SERDES and user logic.

The derive_pll_clocks command prints an Info message to show each generated clock the command creates.

As an alternative to derive_pll_clocks you can copy-and-paste each create_generated_clock assignment into the .sdc file. However, if you subsequently modify the PLL setting, you must also change the generated clock constraint in the .sdc file. Examples of this type of change include modifying an existing output clock, adding a new PLL output, or making a change to the PLL's hierarchy. Use of derive_pll_clocks eliminates this requirement.