2.3.1. Recommended Initial SDC Constraints 2.3.2. SDC File Precedence 2.3.3. Iterative Constraint Modification 2.3.4. Creating Clocks and Clock Constraints 2.3.5. Creating I/O Constraints 2.3.6. Creating Delay and Skew Constraints 2.3.7. Creating Timing Exceptions 2.3.8. Example Circuit and SDC File
220.127.116.11.1. Default Multicycle Analysis 18.104.22.168.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 22.214.171.124.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 126.96.36.199.4. Same Frequency Clocks with Destination Clock Offset 188.8.131.52.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 184.108.40.206.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 220.127.116.11.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 18.104.22.168.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.4.2. Collection Commands
The Timing Analyzer supports collection commands that provide easy access to ports, pins, cells, or nodes in the design. Use collection commands with any constraints or Tcl commands specified in the Timing Analyzer.
|all_clocks||All clocks in the design|
|all_inputs||All input ports in the design.|
|all_outputs||All output ports in the design.|
|all_registers||All registers in the design.|
|get_cells||Cells in the design. All cell names in the collection match the specified pattern. Wildcards can be used to select multiple cells at the same time.|
|get_clocks||Lists clocks in the design. When used as an argument to another command, such as the -from or -to of set_multicycle_path, each node in the clock represents all nodes clocked by the clocks in the collection. The default uses the specific node (even if the node is a clock) as the target of a command.|
|get_nets||Nets in the design. All net names in the collection match the specified pattern. You can use wildcards to select multiple nets at the same time.|
|get_pins||Pins in the design. All pin names in the collection match the specified pattern. You can use wildcards to select multiple pins at the same time.|
|get_ports||All ports (design inputs and outputs) in the design.|
You can also examine collections and experiment with collections using wildcards in the Timing Analyzer by clicking Name Finder from the View menu.
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