Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents Timing Constraint Precedence

If the same clock or node names occur in multiple timing exceptions, the Timing Analyzer observes the following order of timing constraint precedence:
  1. Set False Path (set_false_path) is the first priority
  2. Set Minimum Delay (set_min_delay) and Set Maximum Delay (set_max_delay) are the second priority.
  3. Set Multicycle Path (set_multicycle_path) is the third priority.
The false path timing exception has the highest precedence. Within each category, assignments to individual nodes have precedence over assignments to clocks. For exceptions of the same type:
  1. -from <node> is the first priority.
  2. -to <node> is the second priority.
  3. -thru <node> is the third priority.
  4. -from <clock> is the fourth priority.
  5. -to <clock> is the fifth priority.
An asterisk wildcard (*) for any of these options applies the same precedence as not specifying the option at all. For example, -from a -to * is treated identically to -from a with regards precedence.
Precedence example:
  1. set_max_delay 1 -from x -to y
  2. set_max_delay 2 -from x
  3. set_max_delay 3 -to y

The first exception has higher priority than either of the other two, since the first exception specifies a -from (while #3 doesn't) and specifies a -to (while #2 doesn't). In the absence of the first exception, the second exception has higher priority than the third, since the second exception specifies a -from, which the third does not. Finally, the remaining order of precedence for additional exceptions is order-dependent, such that the assignments most recently created overwrite, or partially overwrite, earlier assignments.

set_net_delay or set_max_skew exceptions analyze independently of minimum or maximum delays, or multicycle path constraints.
  • The set_net_delay exception applies regardless the existence of a set_false_path exception, or set_clock_group exception, on the same nodes.
  • When targeting the Intel® Arria® 10 device or Intel® Cyclone® 10 device and using the 18.1 version of the Timing Analyzer, the set_max_skew exception applies regardless of any set_clock_group exception on the same nodes, but a set_false_path exception overrides a set_max_skew exception.