18.104.22.168.4. Same Frequency Clocks with Destination Clock Offset
The following example shows a design with the same frequency clocks and a destination clock offset.
The following timing diagram shows the default setup check analysis that the Timing Analyzer performs.
The setup relationship shown is too pessimistic and is not the setup relationship required for typical designs. To adjust the default analysis, you assign an end multicycle setup exception of two. The following shows a multicycle exception that adjusts the default analysis:
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \ -setup -end 2
The following timing diagram shows the preferred setup relationship for this example:
The following timing diagram shows the default hold check analysis that the Timing Analyzer performs with an end multicycle setup value of two.
In this example, the default hold analysis returns the preferred hold requirements and no multicycle hold exceptions are required.
The associated setup and hold analysis if the phase shift is –2 ns. In this example, the default hold analysis is correct for the negative phase shift of 2 ns, and no multicycle exceptions are required.
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