ID 683068
Date 9/24/2018
Public

## 2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset

In this example, the source and destination clocks have the same frequency, but the destination clock is offset with a positive phase shift. Both the source and destination clocks have a period of 10 ns. The destination clock has a positive phase shift of 2 ns with respect to the source clock.

The following example shows a design with the same frequency clocks and a destination clock offset.

Figure 78. Same Frequency Clocks with Destination Clock Offset Diagram

The following timing diagram shows the default setup check analysis that the Timing Analyzer performs.

Figure 79. Setup Timing Diagram
Figure 80. Setup Check Calculation

The setup relationship shown is too pessimistic and is not the setup relationship required for typical designs. To adjust the default analysis, you assign an end multicycle setup exception of two. The following shows a multicycle exception that adjusts the default analysis:

### Multicycle Constraint

set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \
-setup -end 2

The following timing diagram shows the preferred setup relationship for this example:

Figure 81. Preferred Setup Relationship

The following timing diagram shows the default hold check analysis that the Timing Analyzer performs with an end multicycle setup value of two.

Figure 82. Default Hold Check
Figure 83. Hold Check Calculation

In this example, the default hold analysis returns the preferred hold requirements and no multicycle hold exceptions are required.

The associated setup and hold analysis if the phase shift is –2 ns. In this example, the default hold analysis is correct for the negative phase shift of 2 ns, and no multicycle exceptions are required.

Figure 84. Negative Phase Shift

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