ID 683068
Date 9/24/2018
Public

## 2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1

In this example, the end multicycle setup assignment value is two, and the end multicycle hold assignment value is one.

### Multicycle Constraint

set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \
-setup -end 2
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -hold -end 1

In this example, the setup relationship relaxes by two clock periods by moving the latch edge to the left two clock periods. The hold relationship relaxes by a full period by moving the latch edge to the previous latch edge.

The following shows the setup timing diagram for the analysis that the Timing Analyzer performs:

Figure 72. Setup Timing Diagram
Figure 73. Setup Check Calculation

The most restrictive hold relationship with an end multicycle setup assignment value of two is 20 ns.

The following shows the setup report for this example in the Timing Analyzer and highlights the launch and latch edges.

Figure 74. Setup Report

The following shows the timing diagram for the hold checks for this example. The hold checks are relative to the setup check.

Figure 75. Hold Timing Diagram
Figure 76. Hold Check Calculation

The most restrictive hold relationship with an end multicycle setup assignment value of two and an end multicycle hold assignment value of one is 0 ns.

The following shows the hold report for this example in the Timing Analyzer and highlights the launch and latch edges.

Figure 77. Hold Report