Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents

2.2.4. Step 4: Run Timing Analysis

After specifying initial timing constraints, you can run the Fitter or full compilation to generate the timing netlist and run the Timing Analyzer. During compilation, the Fitter attempts to place logic of your design to comply with the timing constraints that you specify. The Timing Analyzer reports the margin (slack) by which your design meets or fails each constraint.
  1. To generate the timing netlist, perform either of the following:
    • To run full compilation that includes timing analysis, click Processing > Start Compilation. The Timing Analyzer automatically performs multi-corner signoff timing analysis after the Fitter completes.


    • To run the Fitter, click Processing > Start > Start Fitter.
  2. To launch the Timing Analyzer, click Tools > Timing Analyzer.
  3. In the Tasks pane, double-click Update Timing Netlist. The Timing Analyzer loads the timing netlist, reads all of the project's .sdc files, and generates a default set of timing reports, including the Timing Analyzer Summary and Advanced I/O Timing reports.
    Figure 36. Timing Analyzer Tasks
  4. In the In the Tasks pane, under Reports, double-click any individual task to generate the report and analyze the results, as Step 5: Analyze Timing Analysis Results describes.