Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents Output Constraints (set_output_delay)

Output constraints specify all external delays from the device for all output ports in your design.
set_output_delay -clock { clock } -clock_fall -rise -max 2 foo

Use the Set Output Delay (set_output_delay) constraint to specify external output delay requirements. Specify the Clock name (-clock) to reference the virtual or actual clock. When specifying a clock, the clock defines the latching clock for the output port. The Timing Analyzer automatically determines the launching clock inside the device that launches the output data, because all clocks in the device are defined. The following figure is an example of an output delay referencing a virtual clock.

Figure 55. Output Delay Diagram
Figure 56. Output Delay Calculation