Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Document Table of Contents

2.2.3. Step 3: Specify General Timing Analyzer Settings

Before running timing analysis, you can consider and optionally specify the following Timing Analyzer and Compiler settings that have an impact on the analysis results:
Table 4.  Timing Analyzer and Compiler Settings
Setting Description Location
SDC files to include in the project Specifies the name and order of Synopsis Design Constraint (.sdc) files in the project. Assignments > Settings > Timing Analyzer
Report worst-case paths during compilation Displays summary of the worst-case timing paths in the design. Assignments > Settings > Timing Analyzer
Tcl Script File name Specifies the file name for a custom analysis script. You can specify whether to Run default timing analysis before running the custom script. Assignments > Settings > Timing Analyzer
Metastability analysis Specifies how the Timing Analyzer identifies registers as being part of a synchronization register chain for metastability analysis. Assignments > Settings > Timing Analyzer
Enable multicorner support for Timing Analyzer and EDA Netlist Writer Directs the Timing Analyzer to perform multicorner timing analysis by default, which analyzes the design against best-case and worst-case operating conditions. Assignments > Settings > Compilation Process Settings
Optimization Mode Specifies the focus of Compiler optimization efforts during synthesis and fitting. Specify a Balanced strategy, or optimize for Performance, Area, Power, Routability, or Compile Time. Assignments > Settings > Compiler Settings

SDC Constraint Protection

Verifies.sdc constraints in register merging. This option helps to maintain the validity of .sdc constraints through compilation.

Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis)
Synchronization Register Chain Length

Specifies the maximum number of registers in a row that the Compiler considers as a synchronization chain. Synchronization chains are sequences of registers with the same clock and no fan-out in between, such that the first register is fed by a pin, or by logic in another clock domain. The Compiler considers these registers for metastability analysis. The Compiler prevents optimizations of these registers, such as retiming. When gate-level retiming is enabled, the Compiler does not remove these registers. The default length is set to two.

Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis)

Optimize Design for Metastability

This setting improves the reliability of the design by increasing its Mean Time Between Failures (MTBF). When you enable this setting, the Fitter increases the output setup slacks of synchronizer registers in the design. This slack can exponentially increase the design MTBF. This option only applies when using the Timing Analyzer for timing-driven compilation. Use the Timing Analyzer report_metastability command to review the synchronizers detected in your design and to produce MTBF estimates.

Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)
Figure 35. Timing Analyzer Settings