Visible to Intel only — GUID: mwh1410383726085
Ixiasoft
2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
Visible to Intel only — GUID: mwh1410383726085
Ixiasoft
2.3.4.5.1. Exclusive Clock Groups (-exclusive)
Use the -exclusive option to declare that two clocks are mutually exclusive. You can declare clocks as mutually exclusive if you define multiple clocks are for the same node. This case occurs for multiplexed clocks.
For example, a input port may be clocked by either a 25-MHz or a 50-MHz clock. To constrain this port, create two clocks on the port, and then create clock groups that declare that the clocks do not coexist in the design. Declaring the clocks as mutually exclusive eliminates clock transfers that are derived between the 25-MHz clock and the 50-MHz clock.
Figure 51. Clock Mux with Synchronous Path Across the Mux
create_clock -period 40 -name clk_a [get_ports {port_a}] create_clock -add -period 20 -name clk_b [get_ports {clk_a}] set_clock_groups -exclusive -group {clk_a} -group {clk_b}
Did you find the information on this page useful?
Feedback Message
Characters remaining: