P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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3.2.2.5. Registers

The following VirtIO capability structure registers references apply to each PF and VF. Addresses shown are register addresses.

Table 16.  PF/VF Capability Link List
Capability Start Byte Address Last Byte Address DW Count
Type0 0x00 0x3F 16
PM (PF only) 0x40 0x47 2
VirtIO Common Configuration 0x48 0x57 4
VirtIO Notifications 0x58 0x6B 5
Reserved 0x6C 0x6F 1
PCIe 0x70 0xA3 13
Reserved 0xA4 0xAF 3
MSIX 0xB0 0xBB 3
VirtIO ISR Status 0xBC 0xCB 4
VirtIO Device-Specific Configuration 0xCC 0xDB 4
VirtIO PCI Configuration Access 0xDC 0xEF 5
Reserved 0xF0 0xFF 4
Table 17.  VirtIO Common Configuration Capability Structure
Address Name Description
012 Common Configuration Capability Register Capability ID, next capability pointer, capability length
013 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
014 BAR Offset Register Indicates starting address of the structure within the BAR
015 Structure Length Register Indicates length of structure
VirtIO Notifications Capability Structure
016 Notifications Capability Register Capability ID, next capability pointer, capability length
017 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
018 BAR Offset Register Indicates starting address of the structure within the BAR
019 Structure Length Register Indicates length of structure
01A Notify Off Multiplier Multiplier for queue_notify_off
VirtIO ISR Status Capability Structure
02F ISR Status Capability Register Capability ID, next capability pointer, capability length
030 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
031 BAR Offset Register Indicates starting address of the structure within the BAR
032 Structure Length Register Indicates length of structure
VirtIO Device-Specific Capability Structure (Optional)
033 Device Specific Capability Register Capability ID, next capability pointer, capability length
034 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
035 BAR Offset Register Indicates starting address of the structure within the BAR
036 Structure Length Register Indicates length of structure
VirtIO PCI Configuration Access Structure
037 PCI Configuration Access Capability Register Capability ID, next capability pointer, capability length
038 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
039 BAR Offset Register Indicates starting address of the structure within the BAR
03A Structure Length Register Indicates length of structure
03B PCI Configuration Data Data for BAR access

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