P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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4.4.5. Avalon® -ST TX Interface

The Application Layer transfers data to the Transaction Layer of the PCI Express* IP core over the Avalon® -ST TX interface. The Transaction Layer must assert tx_st_ready_o before transmission begins. Transmission of a packet must be uninterrupted when tx_st_ready_o is asserted.

This 512-bit interface supports two locations for the beginning of a TLP, bit[0] and bit[256]. The interface supports multiple TLPs per cycle only when an end-of-packet cycle occurs in the lower 256 bits.

Note: This interface supports two tx_st_sop_i signals and two tx_st_eop_i signals per cycle when the P-Tile IP is operating in a x16 configuration. It also does not follow a fixed latency between the tx_st_ready_o and tx_st_valid_i[1:0] signals. Data can be received any time within the defined readyLatency, which is three coreclkout_hip cycles.

The x16 core provides two segments with each one having 256 bits of data (tx_st_data_i[511:256] and tx_st_data_i[255:0]), 128 bits of header (tx_st_hdr_i[255:128] and tx_st_hdr_i[127:0]), and 32 bits of TLP prefix (tx_st_tlp_prfx_i[63:32] and tx_st_tlp_prfx_i[31:0]). If this core is configured in the 1x16 mode, both segments are used, so the data bus becomes a 512-bit bus tx_st_data_i[511:0]. The start of packet can appear in the upper segment or lower segment, as indicated by the tx_st_sop_i[1:0] signals.

Note: To achieve the expected performance in Gen4 x16 mode, the user application needs to take advantage of this segmented bus architecture. Otherwise, some performance reduction may occur.

If this core is configured in the 2x8 mode, only the lower segment is used. In this case, the data bus is a 256-bit bus tx_st_data_i[255:0].

Finally, if this core is configured in the 4x4 mode, only the lower segment is used and only the LSB 128 bits of data are valid. In this case, the data bus is a 128-bit bus tx_st_data_i[127:0].

The x8 core provides one segment with 256 bits of data, 128 bits of header and 32 bits of TLP prefix. If this core is configured in 4x4 mode, only the LSB 128 bits of data are used.

The x4 core provides one segment with 128 bits of data, 128 bits of header and 32 bits of TLP prefix.

Table 55.   Avalon® -ST TX Interface
Signal Name Direction Description Clock Domain EP/RP/BP

x16: tx_st_data_i[511:0]

x8: tx_st_data_i[255:0]

x16: tx_st_data_i[127:0]

I

Application Layer data for transmission. The Application Layer must provide a properly formatted TLP on the TX interface. Valid when the corresponding tx_st_valid_i signal is asserted.

The mapping of message TLPs is the same as the mapping of Transaction Layer TLPs with 4-dword headers. The number of data cycles must be correct for the length and address fields in the header. Issuing a packet with an incorrect number of data cycles results in the TX interface hanging and becoming unable to accept further requests.

Note: There must be no Idle cycle between the tx_st_sop_i and tx_st_eop_i cycles unless there is backpressure with the deassertion of tx_st_ready_o.
coreclkout_hip EP/RP/BP

x16: tx_st_sop_i[1:0]

x8/x4: tx_st_sop_i

I
Indicate the first cycle of a TLP when asserted in conjunction with the corresponding bit of tx_st_valid_i. For the x16 configuration:
  • tx_st_sop_i[1]: When asserted, indicates the start of a TLP in tx_st_data_i[511:256].
  • tx_st_sop_i[0]: When asserted, indicates the start of a TLP in tx_st_data_i[255:0].

These signals are asserted for one clock cycle per each TLP. They also qualify the corresponding tx_st_hdr_i and tx_st_tlp_prfx_i signals.

coreclkout_hip EP/RP/BP

x16: tx_st_eop_i[1:0]

x8/x4: tx_st_eop_i

I
Indicate the last cycle of a TLP when asserted in conjunction with the corresponding bit of tx_st_valid_i. For the x16 configuration:
  • tx_st_eop_i[1]: When asserted, indicates the end of a TLP in tx_st_data_i[511:256].
  • tx_st_eop_i[0]: When asserted, indicates the end of a TLP in tx_st_data_i[255:0].

These signals are asserted for one clock cycle per each TLP.

coreclkout_hip EP/RP/BP

x16: tx_st_valid_i[1:0]

x8/x4: tx_st_valid_i

I

Qualify the corresponding data segment of tx_st_data_i into the IP core on ready cycles.

To facilitate timing closure, Intel recommends that you register both the tx_st_ready_o and tx_st_valid_i signals.

Note: There must be no Idle cycle between the tx_st_sop_i and tx_st_eop_i cycles unless there is backpressure with the deassertion of tx_st_ready_o.
coreclkout_hip EP/RP/BP
tx_st_ready_o O

Indicates that the PCIe Hard IP is ready to accept data for transmission.

The readyLatency is three cycles.

If tx_st_ready_o is asserted by the Transaction Layer in the PCIe Hard IP on cycle <n>, then <n> + readyLatency is a ready cycle, during which the Application may assert tx_st_valid_i and transfer data.

If tx_st_ready_o is deasserted by the Transaction Layer on cycle <n>, then the Application must deassert tx_st_valid_i within the readyLatency number of cycles after cycle <n>.

tx_st_ready_o can be deasserted in the following conditions:
  • The LTSSM is not ready.
  • A Retry is in progress.
  • There are not enough credits available to send the request.
  • The P-Tile Avalon-ST IP is busy sending internally generated TLPs.
  • The internal P-Tile TX FIFO is full.
coreclkout_hip EP/RP/BP

x16: tx_st_err_i[1:0]

x8/x4: tx_st_err_i

I
When asserted, indicate an error in the transmitted TLP. These signals are asserted with tx_st_eop_i and nullify a packet.
  • tx_st_err_i[1]: When asserted, specifies an error in tx_st_data_i[511:256].
  • tx_st_err_i[0]: When asserted, specifies an error in tx_st_data_i[255:0].
coreclkout_hip EP/RP/BP

x16: tx_st_hdr_i[255:0]

x8/x4: tx_st_hdr_i[127:0]

I
This is the header to be transmitted, which follows the TLP header format of the PCIe specifications except for the requester ID/completer ID fields (tx_st_hdr_i[95:80]):
  • tx_st_hdr_i[95:84]: tx_st_vf_num[11:0]
  • tx_st_hdr_i[83]: tx_st_vf_active
  • tx_st_hdr_i[82:80]: tx_st_func_num[2:0]

A valid function number must be provided to tx_st_hdr_i[82:80]. When SR-IOV is not enabled, tx_st_hdr_i[83] field must be set to low, tx_st_hdr_i[95:84] can be set to any value.

These signals are valid when the corresponding tx_st_sop_i signal is asserted.

The header uses a Big Endian implementation.

coreclkout_hip EP/RP/BP

x16: tx_st_tlp_prfx_i[63:0]

x8/x4: tx_st_tlp_prfx_i[31:0]

I

This is the TLP prefix to be transmitted, which follows the TLP prefix format of the PCIe specifications. PASID is included.

These signals are valid when the corresponding tx_st_sop_i signal is asserted.

The TLP prefix uses a Big Endian implementation (i.e. the Fmt field is in bits [31:29] and the Type field is in bits [28:24]).

If no prefix is present for a given TLP, that dword, including the Fmt field, is all zeros.

coreclkout_hip EP/RP/BP

x16: tx_st_data_par_i[63:0]

x8: tx_st_data_par_i[31:0]

x4: tx_st_data_par_i[15:0]

I

Byte parity for tx_st_data_i. Bit [0] corresponds to tx_st_data_i[7:0], bit [1] corresponds to tx_st_data_i[15:8], and so on.

By default, the PCIe Hard IP generates the parity for the TX data. Any parity bytes provided on these signals will not be used by the PCIe Hard IP for the parity generation and checking.

coreclkout_hip EP/RP/BP

x16: tx_st_hdr_par_i[31:0]

x8/x4: tx_st_hdr_par_i[15:0]

I

Byte parity for tx_st_hdr_i.

By default, the PCIe Hard IP generates the parity for the TX header. Any parity bytes provided on these signals will not be used by the PCIe Hard IP for the parity generation and checking.

coreclkout_hip EP/RP/BP

x16: tx_st_tlp_prfx_par_i[7:0]

x8/x4: tx_st_tlp_prfx_par_i[3:0]

I

Byte parity for tx_st_tlp_prfx_i.

By default, the PCIe Hard IP generates the parity for the TX TLP prefix. Any parity bytes provided on these signals will not be used by the PCIe Hard IP for the parity generation and checking.

coreclkout_hip EP/RP/BP
tx_par_err_o O Asserted for a single cycle to indicate a parity error during TX TLP transmission. The IP core transmits TX TLP packets even when a parity error is detected. coreclkout_hip EP/RP/BP
Figure 23.  Avalon® -ST TX Packet Interface in 1x16 Mode
Figure 24.  Avalon® -ST TX Packet Interface in 2x8 Mode
Note: In 2x8 mode, the pn prefix in the signal names is p0 and p1 for the two x8 ports.
Figure 25.  Avalon® -ST TX Packet Interface in 4x4 Mode
Note: In 4x4 mode, the pn prefix in the signal names is p0, p1, p2 and p3 for the four x4 ports.
Note: In the diagrams for the 1x16 or 2x8 modes, D0_0 represents a 256-bit block of data. However, in the diagram for the 4x4 mode, D0_0 represents a 128-bit block of data.

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