P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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F.2. P-tile PCIe Design Constraints

The following signals are available for resetting P-tile:
  • pin_perst_n: This is a global full reset. It resets the PHY and port controllers.
  • pld_clrpcs_n[1:0]: These are per-port resets, which will reset only the PCS and port controllers. These signals do not reset the PHY.
  • pld_clrphy_n[1]: This signal is only applicable to Port 1. It resets the PCS, PHY and port controller. It is available when the option Port 1 refclk init active is disabled in the IP Parameter Editor.
P-tile has the following design considerations and constraints when two-endpoint configurations are connected to independent systems/Hosts.
  • Constraint 1: The P-tile EMIB interface operates all ports on a common system clock domain associated with PCIe Port 0. Hence, the PCIe Port 0 must be the primary endpoint.
  • Constraint 2a: Port 0's reference clock must be active prior to the first pin_perst_n deassertion (i.e. cold reset exit), and should remain active while the FPGA has power (VCC_HSSI).
    • Note that this typically occurs during the FPGA's initial configuration.
  • Constraint 2b: Port 1's reference clock may be active prior to the first pin_perst_n deassertion (Type D only).
  • Constraint 3: In PCIe modes, pin_perst_n is expected to be implemented as a "full reset", which causes a global reset and in turn reruns PHY calibration-related operations.
  • Constraint 4: P-tile expects the reference clock for Port 0 to remain active during subsequent warm reset assertions.

  • Constraint 5: Implementing the independent PERST# solution will lock out the PHY Reconfiguration interface. User application logic cannot drive this interface when independent PERST# is implemented.
    • The Debug Toolkit also cannot be used.
    • The Hard IP Reconfiguration interface is still available.

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