P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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E.2.1. Avalon® -ST PCIe PIO Example Design

In the Avalon® -ST PCIe IP GUI, configure the Avalon® -ST PCIe IP as a Gen4 x16 Endpoint and generate the example design. This example design automatically creates the files for simulation. Following is the top-level testbench block diagram showing the default Root Port BFM and PIO example design.

Figure 98. PCIe PIO Example Design Simulation Testbench

For details on the example design generation, refer to the Quick Start Guide chapter of the Intel FPGA P-Tile Avalon® -ST IP for PCI Express User Guide.

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