P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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Document Table of Contents

1.2. Features

The P-tile Avalon® streaming IP for PCI Express* supports the following features:

PCIe* Features:
  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as a Hard IP.
  • Configurations supported:
    Table 1.  Configurations Supported by the P-Tile Avalon® streaming IP for PCI Express
      Gen3/Gen4 x16 Gen3/Gen4 x8 Gen3/Gen4 x4
    Endpoint (EP) Yes Yes N/A
    Root Port (RP) Yes N/A Yes
    TLP Bypass Yes Yes Yes
    Note: Gen1/Gen2 configurations are supported via link down-training.
  • Static port bifurcation (four x4s Root Port, two x8s Endpoint).
  • Supports TLP Bypass mode.
    • Supports one x16, two x8, or four x4 interfaces.
    • Supports upstream/downstream TLP bypass mode.
  • Supports up to 512-byte maximum payload size (MPS).
  • Supports up to 4096-byte (4 KB) maximum read request size (MRRS).
  • Single Virtual Channel (VC).
  • Page Request Services (PRS).
  • Completion Timeout Ranges.
  • Atomic Operations (FetchAdd/Swap/CAS).
  • Extended Tag Support.
    • 10-bit Tag Support (Port 0 x16 Controller only)
  • Separate Refclk with Independent Spread Spectrum Clocking (SRIS).
  • Separate Refclk with no Spread Spectrum Clocking (SRNS).
  • Common Refclk architecture.
  • PCI Express* Advanced Error Reporting (PF only).
    Note: Advanced Error Reporting is always enabled in the P-Tile Avalon® streaming IP for PCIe.
  • ECRC generation and checking.
  • Data bus parity protection.
  • Supports D0 and D3 PCIe power states.
  • Lane Margining at Receiver.
  • Retimers presence detection.
Multifunction and Virtualization Features:
  • SR-IOV support (8 PFs, 2K VFs per each Endpoint).
  • Access Control Service (ACS) capability.
    Note: For ACS, only ports 0 and 1 are supported.
  • Alternative Routing-ID Interpretation (ARI).
  • Function Level Reset (FLR).
  • TLP Processing Hint (TPH).
    Note: TPH supports the "No Steering Tag (ST)" mode only.
  • Address Translation Services (ATS). (For more information, refer to Implementation of Address Translation Services (ATS) in Endpoint Mode).
  • Process Address Space ID (PasID).
  • Configuration Intercept Interface (CII).
IP Features:
  • User packet interface with separate header, data and prefix.
  • User packet interface with a split-bus architecture where the header, data and prefix busses consist of two segments each (x16 mode only). This improves the bandwidth efficiency of this interface as it can handle up to 2 TLPs in any given cycle.
  • Maximum numbers of outstanding Non-Posted requests (NPRs) supported when 8-bit tags or 10-bit tags are enabled are summarized in the table below:
    Table 2.  Outstanding Non-Posted Requests Supported
    Ports Active Cores 8-bit Tags 10-bit Tags
    0 x16 256 512 (*)
    1 x8 256 N/A
    2 and 3 x4 256 N/A
    Note: (*): Use tags 256 to 767.
  • Completion timeout interface.
    • The PCIe Hard IP can optionally track outgoing non-posted packets to report completion timeout information to the application.
  • You cannot change the pin allocations for the P-Tile Avalon® streaming IP for PCI Express* in the Intel® Quartus® Prime project. However, this IP does support lane reversal and polarity inversion on the PCB by default.
  • Supports Autonomous Hard IP mode.
    • This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into User mode are complete.
      Note: Unless Readiness Notifications mechanisms are used, the Root Complex and/or system software must allow at least 1.0 s after a Conventional Reset of a device before it may determine that a device that fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
  • FPGA core configuration via PCIe link (CvP Init and CvP Update).
    Note: CvP Init and CvP Update are available for Intel® Stratix® 10 DX devices. For Intel® Agilex™ devices, CvP Init is available, and CvP Update will be available in a future Intel® Quartus® Prime release.
    Note: For Gen3 and Gen4 x16 variants, Port 0 (corresponding to lanes 0 - 15) supports the CvP features. For Gen3 and Gen4 x8 variants, only Port 0 (corresponding to lanes 0 - 7) supports the CvP features. Port 1 (corresponding to lanes 8 - 15) does not support CvP.
  • Device-dependent PLD clock (coreclkout_hip) frequency.
    • 350 MHz / 400 MHz / 450 MHz for Intel® Stratix® 10 DX devices, 350 MHz / 400 MHz / 450 MHz / 500 MHz for Intel® Agilex™ devices.
  • P-Tile Debug Toolkit including the following features:
    • Protocol and link status information.
    • Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.
  • Riviera*, Siemens EDA QuestaSim* and VCS* are the simulators supported in the 22.1 release of Intel® Quartus® Prime. Other simulators may be supported in a future release.
Note: Throughout this User Guide, the term Avalon-ST may be used as an abbreviation for the Avalon® streaming interface or IP.

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