P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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Document Table of Contents

4.12.1. Address Map for the User Avalon-MM Interface

Figure 42. Address Map for the User Avalon® -MM Interface
Table 77.  Configuration Space Offsets
Registers User Avalon® -MM Offsets Comments
Physical function 0 0x0000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16, x8 and x4 cores.
Physical function 1 0x1000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16 and x8 cores only.
Physical function 2 0x2000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16 and x8 cores only.
Physical function 3 0x3000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16 and x8 cores only.
Physical function 4 0x4000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16 and x8 cores only.
Physical function 5 0x5000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16 and x8 cores only.
Physical function 6 0x6000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16 and x8 cores only.
Physical function 7 0x7000 Refer to Appendix A for more details of the PF configuration space. This PF is available for x16 and x8 cores only.
User Avalon-MM Control Register 0x104068 Refer to User Avalon-MM Control Register (Offset 0x104068) for more details.
Debug (DBI) Register 0x104200 to 0x104204 Refer to Using the Debug Register Interface Access (Dword Access) for more details.
Note: The x4 configuration only supports the RP mode. Therefore, this configuration does not support the multi-function feature.

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