P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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4.14. Page Request Service (PRS) Interface (EP Only)

When an Endpoint determines that it requires access to a page for which the ATS translation is not available, it sends a Page Request message to request that the page be mapped into system memory.

The PRS interface allows the monitoring of when PRS events happen, what functions these PRS events belong to, and what types of events they are.

The PRS interface is only available in EP mode, and with TLP Bypass disabled.

Note: The P-Tile Avalon® -ST IP for PCIe only provides the PRS capability. To take advantage of this feature, you need to implement the necessary logic in your application.
Note: In the Intel® Quartus® Prime 20.3 release, only PF0 supports PRS. Furthermore, in this release, the PRS interface only has Compilation (C) and Simulation (S) support.
Table 82.  PRS Interface Signals
Signal Name Direction Description Clock Domain EP/RP/BP
prs_event_valid_i I This signal qualifies prs_event_func_i and prs_event_i. There is a single-cycle pulse for each PRS event. coreclkout_hip EP
prs_event_func_i[2:0] I The function number for the PRS event. coreclkout_hip EP
prs_event_i[1:0] I

00 : Indicate that the function has received a PRG response failure.

01: Indicate that the function has received a response with Unexpected Page Request Group Index.

10: Indicate that the function has completed all previously issued page requests and that it has stopped requests for additional pages. Only valid when the PRS enable bit is clear.

11: reserved.

coreclkout_hip EP

The figure below shows the timing diagram for the PRS event interface when the application layer of function 0 sends an event of PRG response reception, and the application layer of function 1 sends an event stopping requests for additional pages.

Figure 49. Example Timing Diagram for the PRS Event Interface

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