P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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7.1.1.2. Signal Tap II Logic Analyzer

Using the Signal Tap II Logic Analyzer, you can monitor the following top-level signals from the P-Tile Avalon® -ST IP for PCI Express to confirm the failure symptom for any port type (Root Port, Endpoint or TLP Bypass) and configuration (Gen4/Gen3).

Table 111.  Top-Level Signals to be Monitored for Debugging
Signals Description Expected Value for Successful Link-up
p<n>_pin_perst_n where n = 0, 1, 2, 3

Active-low asynchronous output signal from the PCIe Hard IP. It is derived from the pin_perst_n input signal.

1'b1
p<n>_reset_status_n where n = 0, 1, 2, 3

Active-low output signal from the PCIe Hard IP, synchronous to coreclkout_hip.

Held low until pin_perst_n is deasserted and the PCIe Hard IP comes out of reset, synchronous to coreclkout_hip.

When port bifurcation is used, there is one such signal for each Avalon® -ST interface.

1'b1
ninit_done

Active-low output signal from the Reset Release Intel FPGA IP. High indicates that the FPGA device is not yet fully configured, and low indicates the device has been configured and is in normal operating mode.

For more details on the Reset Release Intel FPGA IP, refer to https://www.intel.com/content/www/us/en/programmable/documentation/prh1555609801770.html

1'b0
link_up_o

Active-high output signal from the PCIe Hard IP, synchronous to coreclkout_hip.

Indicates that the Physical Layer link is up.

1'b1
dl_up_o

Active-high output signal from the PCIe Hard IP, synchronous to coreclkout_hip.

Indicates that the Data Link Layer is active.

1'b1
ltssm_state_o[5:0]

Indicates the LTSSM state, synchronous to coreclkout_hip.

6'h11 (L0)

Negotiated link speed using the Transaction Layer Configuration Output interface (tl_cfg):

tl_cfg_add_o[4:0]

tl_cfg_ctl_o[15:12]

tl_cfg_func_o[2:0]

Use the Transaction Layer Configuration Output interface (tl_cfg) to monitor the auto-negotiated link speed.

tl_cfg_add_o[4:0] = 5'h05

tl_cfg_ctl_o[15:12] =
  • 4’h01 (Gen1)
  • 4’h02 (Gen2)
  • 4’h04 (Gen3)
  • 4’h08 (Gen4)
tl_cfg_func_o[2:0] (NA for x4) =
  • 3’b000: PF0
  • 3'b001: PF1, etc.

Negotiated link width using the Transaction Layer Configuration Output interface (tl_cfg):

tl_cfg_add_o[4:0]

tl_cfg_ctl_o[15:12]

tl_cfg_func_o[2:0]

Use the Transaction Layer Configuration Output interface (tl_cfg) to monitor the auto-negotiated link width.

tl_cfg_add_o[4:0] = 5'h1C

tl_cfg_ctl_o[5:0] =
  • 6’h01 (x1)
  • 6’h02 (x2)
  • 6’h04 (x4)
  • 6’h08 (x8)
  • 6'h10 (x16)

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