P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.3.5.5. ebfm_cfgwr_imm_wait Procedure

The ebfm_cfgwr_imm_wait procedure writes up to four bytes of data to the specified configuration register. This procedure waits until the write completion has been returned.

Location

Syntax

ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num, imm_regb_ad, regb_ln, imm_data, compl_status

Arguments

bus_num

PCI Express bus number of the target device.

dev_num

PCI Express device number of the target device.

fnc_num

Function number in the target device to be accessed.

regb_ad

Byte-specific address of the register to be written.

regb_ln

Length, in bytes, of the data written. Maximum length is four bytes. The regb_ln and the regb_ad arguments cannot cross a DWORD boundary.

imm_data

Data to be written.

This argument is reg [31:0].

The bits written depend on the length:

  • 4: 31 down to 0
  • 3: 23 down to 0
  • 2: 15 down to 0
  • 1: 7 down to 0
compl_status

This argument is reg [2:0].

This argument is the completion status as specified in the PCI Express specification. The following encodings are defined:

  • 3’b000: SC— Successful completion
  • 3’b001: UR— Unsupported Request
  • 3’b010: CRS — Configuration Request Retry Status
  • 3’b100: CA — Completer Abort

Did you find the information on this page useful?

Characters remaining:

Feedback Message