5.2.5. Configuration, Debug and Extension Options
|Gen 3 Requested equalization far-end TX preset vector||0 - 65535||0x00000004||Specifies the Gen 3 requested phase 2/3 far-end TX preset vector. Choosing a value different from the default is not recommended for most designs.|
|Gen 4 Requested equalization far-end TX preset vector||0 - 65535||0x00000270||Specifies the Gen 4 requested phase 2/3 far-end TX preset vector. Choosing a value different from the default is not recommended for most designs.|
|Enable RX Buffer Limit Ports||True/False||False||When selected, RX buffer limit ports are exported allowing you to control the buffer limits for RX Posted, Non-Posted and CplD packets. Otherwise, the Maximum Buffer Size is used.|
|Port 1 REFCLK Init Active||True/False||True||
If this parameter is True (default), the refclk1 is stable after pin_perst and is free-running. This parameter must be set to True for Type A/B/C systems.
If this parameter is False, refclk1 is only available later in User Mode. This parameter must be set to False for Type D systems.
This parameter is only available in the PCIe1 Settings tab for a X8X8 topology.
Note: Refer to Appendix E for more details regarding the bifurcation feature and its usage.
|Strip ECRC||True/False||False||Strip off the ECRC field from the TLP payload when the TD bit is set. Note that this option is only available in the TLP-Bypass mode.|
|Enable HIP dynamic reconfiguration of PCIe* registers||True/False||False||Enable the user Hard IP reconfiguration Avalon® -MM interface.|
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