P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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3.2.1.4. Function Level Reset (FLR)

Use the FLR interface to reset individual SR-IOV functions. The PCIe* Hard IP supports FLR for both PFs and VFs. If the FLR is for a specific VF, the received packets for that VF are no longer valid. The flr_* interface signals are provided to the application interface for this purpose. When the flr_rcvd* signal is asserted, it indicates that an FLR is received for a particular PF/VF. Application logic needs to perform its FLR routine and send the completion status back on the flr_completed* interface. The Hard IP will wait for the flr_completed* status to re-enable the VF. Prior to that event, the Hard IP will respond to transactions to the function that is reset by the FLR as follows:
  • It will discard all posted requests and return Unsupported Request (UR) for non-posted requests.
  • It will discard completions as Unexpected Completions (UC).

The following figure shows the timing diagram for an FLR event targeting a PF (PF2 in this example):

Figure 9. FLR for PF

Here is the timing diagram for an FLR event targeting a VF:

Figure 10. FLR for VF

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