P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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4.12. Hard IP Reconfiguration Interface

The Hard IP reconfiguration interface is an Avalon® -MM slave interface with a 21‑bit address and an 8‑bit data bus. It is also sometimes referred to as the User Avalon® -MM Interface. You can use this interface to dynamically modify the value of configuration registers. Note that after a warm reset or cold reset, changes made to the configuration registers of the Hard IP via the Hard IP reconfiguration interface are lost as these registers revert back to their default values.

Note: This interface can be used in Endpoint, Root Port and TLP Bypass modes. However, it must be enabled if Root Port or TLP Bypass mode is selected.
Note: For the proper initialization of the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* , the Hard IP reconfiguration interface must not have any activity during the assertion of pin_perst_n.

In Root Port mode, the application logic uses the Hard IP reconfiguration interface to access its PCIe configuration space to perform link control functions (such as Hot Reset, link disable, or link retrain).

In TLP Bypass mode, the Hard IP forwards the received Type0/1 Configuration request TLPs to the application logic, which must respond with Completion TLPs with a status of Successful Completion (SC), Unsupported Request (UR), Configuration Request Retry Status (CRS), or Completer Abort (CA). If a received Configuration request TLP needs to update a PCIe configuration space register, the application logic needs to use the Hard IP reconfiguration interface to access that PCIe configuration space register.

Table 76.  Hard IP Reconfiguration Interface
Signal Name Direction Description Clock Domain EP/RP/BP
hip_reconfig_clk I

Reconfiguration clock

50 MHz - 125 MHz (Range)

100 MHz (Recommended)

  EP/RP/BP
hip_reconfig_readdata_o[7:0] O Avalon® -MM read data outputs hip_reconfig_clk EP/RP/BP
hip_reconfig_readdatavalid_o O Avalon® -MM read data valid. When asserted, the data on hip_reconfig_readdata_o[7:0] is valid. hip_reconfig_clk EP/RP/BP
hip_reconfig_write_i I Avalon® -MM write enable hip_reconfig_clk EP/RP/BP
hip_reconfig_read_i I Avalon® -MM read enable hip_reconfig_clk EP/RP/BP
hip_reconfig_address_i[20:0] I Avalon® -MM address hip_reconfig_clk EP/RP/BP
hip_reconfig_writedata_i[7:0] I Avalon® -MM write data inputs hip_reconfig_clk EP/RP/BP
hip_reconfig_waitrequest_o O When asserted, this signal indicates that the IP core is not ready to respond to a request. hip_reconfig_clk EP/RP/BP
dummy_user_avmm_rst I Reset signal. You can tie it to ground or leave it floating when using the Hard IP Reconfiguration Interface.   EP/RP/BP

Reading and Writing to the Hard IP Reconfiguration Interface

Reading from the Hard IP reconfiguration interface of the P-Tile Avalon® -ST IP for PCI Express retrieves the current value at a specific address. Writing to the reconfiguration interface changes the data value at a specific address. Intel recommends that you perform read-modify-writes when writing to a register, because two or more features may share the same reconfiguration address.

Modifying the PCIe configuration registers directly affects the behavior of the PCIe device.

Figure 41. Timing Diagram to Perform Read and Write Operations Using the Hard IP Reconfiguration Interface

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