P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022

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4.6.2. MSI

MSI interrupts are signaled on the PCI Express link using a single dword Memory Write TLP. The user application issues an MSI request (MWr) through the Avalon® -ST interface and updates the configuration space register using the MSI interface.

For more details on the MSI Capability Structure, refer to MSI Capability Structure.

The Mask Bits register and Pending Bits register are 32 bits in length each, with each potential interrupt message having its own mask bit and pending bit. If bit[0] of the Mask Bits register is set, interrupt message 0 is masked. When an interrupt message is masked, the MSI for that vector cannot be sent. If software clears the mask bit and the corresponding pending bit is set, the function must send the MSI request at that time.

You should obtain the necessary MSI information (such as the message address and data) from the configuration output interface (tl_cfg_*) to create the MWr TLP in the format shown below to be sent via the Avalon® -ST interface.

Figure 31. Creating a MWr TLP for an MSI Request
Table 62.  MSI Pending Bits Interface
Signal Name Direction Description Clock Domain EP/RP/BP
msi_pnd_func_i[2:0] I Function number select for the Pending Bits register in the MSI capability structure. coreclkout_hip EP
msi_pnd_addr_i[1:0] I Byte select for Pending Bits Register in the MSI Capability Structure. For example if msi_pnd_addr_i[1:0] = 00, bits [7:0] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0]. If msi_pnd_addr_i[1:0] = 01, bits [15:8] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0]. coreclkout_hip EP
msi_pnd_byte_i[7:0] I Indicate that function has a pending associated message. coreclkout_hip EP

The following figure shows the timings of msi_pnd_* signals in three scenarios. The first scenario shows the case when the MSI pending bits register is not used. The second scenario shows the case when only physical function 0 is enabled and the MSI pending bits register is used. The last scenario shows the case when two physical functions are enabled and the MSI pending bits register is used.

Figure 32. Example Timing Diagrams for msi_pnd* Signals

There are 32 possible MSI messages. The number of messages requested by a particular component does not necessarily correspond to the number of messages allocated. For example, in the following figure, the Endpoint requests eight MSIs but is only allocated two. In this case, you must design the Application Layer to use only two allocated messages.

Figure 33. MSI Request Example

The following table describes three example implementations. The first example allocates all 32 MSI messages. The second and third examples only allocate 4 interrupts.

Table 63.  MSI Messages Requested, Allocated, and Mapped






System Error




Hot Plug and Power Management Event




Application Layer




MSI interrupts generated for Hot Plug, Power Management Events, and System Errors always use Traffic Class 0. MSI interrupts generated by the Application Layer can use any Traffic Class. For example, a DMA that generates an MSI at the end of a transmission can use the same traffic control as was used to transfer data.

The following figure illustrates a possible implementation of the Interrupt Handler Module with a per vector enable bit in the Application Layer. Alternatively, the Application Layer could implement a global interrupt enable instead of this per vector MSI.

Figure 34. Example Implementation of the Interrupt Handler Block