P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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2.2.1. PMA/PCS

The P-Tile Avalon® -ST IP for PCI Express contains Physical Medium Attachment (PMA) and PCI Express Physical Coding Sublayer (PCIe PCS) blocks for handling the Physical layer (PHY) packets. The PMA receives and transmits high-speed serial data on the serial lanes. The PCS acts as an interface between the PMA and the PCIe controller, and performs functions like data encoding and decoding, scrambling and descrambling, block synchronization etc. The PCIe PCS in the P-Tile Avalon® -ST IP for PCI Express is based on the PHY Interface for PCI Express (PIPE) Base Specification 4.4.1.

In this IP, the PMA consists of up to four quads. Each quad contains a pair of transmit PLLs and four SerDes lanes capable of running up to 16 GT/s to perform the various TX and RX functions.

PLLA generates the required transmit clocks for Gen1/Gen2 speeds, while PLLB generates the required clocks for Gen3/Gen4 speeds. For the x8 and x16 lane widths, one of the quads acts as the master PLL source to drive the clock inputs for each of the lanes in the other quads.

The PMA performs functions such as serialization/deserialization, clock data recovery, and analog front-end functions such as Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE) and transmit equalization.

The transmitter consists of a 3-tap equalizer with one tap of pre-cursor, one tap of main cursor and one tap of post-cursor.

The receiver consists of attenuation (ATT), CTLE, Voltage gain amplifier (VGA) and a 5-tap DFE blocks that are adaptive for Gen3/Gen4 speeds. RX Lane Margining is supported by the PHY. The Lane Margining supports timing margining only. The optional voltage margining is not supported. Timing margining capabilities/parameters are as follows:
  • Maximum Timing Offset: -0.2UI to +0.2UI.
  • Number of timing steps: 9.
  • Independent left and right timing margining is supported.
  • Independent Error Sampler is not supported (lane margining may produce logical errors in the data stream and cause the LTSSM to go to the Recovery state).

The PHY layer uses a fixed 16-bit PCS-PMA interface width to output the PHY clock (core_clk). The frequency of this clock is dependent on the current link speed. Refer to PHY Clock and Application Clock Frequencies for the frequencies at various link speeds.

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