3.3.3. User Avalon® -MM Interface
For more details on the signals in this interface, refer to the section Hard IP Reconfiguration Interface.
The majority of the PCIe standard registers are implemented in the user’s logic outside of the P-Tile Avalon® -ST IP.
- Power management capability
- PCI Express capability
- Secondary PCI Express capability
- Data link feature extended capability
- Physical layer 16.0GT/s extended capability
- Lane margining at the receiver extended capability
- Advanced error reporting capability
The application can only access PCIe controller registers through the User Avalon® -MM interface.
|Power Management Capability||Need to write back since it is required to trigger a PCI-PM entry.|
|PCI Express Capability||All the PCIe capabilities, control and status registers are for configuring the device. Write-back is required.|
|Secondary PCI Express Capability||Secondary PCIe Capability is required for configuring the device.|
|Data Link Feature Extended Capability||Data Link Capability is device specific.|
|Physical Layer 16.0 GT/s Extended Capability||Physical Layer 16G Capability is device specific.|
|Lane Margining at the Receiver Extended Capability||Margining Extended Capability is device specific.|
|Advanced Error Reporting Capability||Write-back to error status registers is required for TLP Bypass.|
- Specify the Device ID and Vendor ID in the IP Parameter Editor and then read them from the PCIe Controller through the User Avalon-MM interface.
- Implement the Device ID and Vendor ID in the user logic.
The remaining registers of the PCIe Configuration Header Registers need to be implemented in the user logic.
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