P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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4.4.8. Tag Allocation

The P-Tile PCIe Hard IP supports the 10-bit tag Requester capability in the x16 Controller (Port 0) only. It supports up to 512 outstanding Non-Posted Requests (NPRs) with valid tag values ranging from 256 to 767.

When the Enable 10-bit tag support interface option is enabled, the IP enables the port p0_10bits_tag_req_en_o [7:0] (one bit per PF) to indicate the 10-bit tag request field is enabled in the configuration space (bit [12] of the Device Control 2 register). For more details, refer to the PCI Express Base Specification Revision 4.0.

Table 57.  Tag Interface
Signal Name Direction Description Clock Domain EP/RP/BP
p0_10bits_tag_req_en_o[7:0] O One bit per PF. Indicates the 10-bit tag request field in the Device Control 2 register of that PF is enabled. coreclkout_hip EP

The x8 (Port 1) and x4 Controllers (Port 2/3) don’t support the 10-bit tag Requester capability, although they support the 10-bit Completer capability.

Both x8 and x4 Controllers can allow up to 256 outstanding NPRs with valid tag values ranging from 0 to 255.

When enabling both 10-bit tags and 8-bit tags, the LSB 8 bits of the 8-bit tags cannot be shared with the LSB 8 bits of the 10-bit tags. For example, if you want to use 64 tags as 8-bit tags and the rest of the tags as 10-bit tags, you can partition the tag space as follows:
  • 8-bit tags : 0 - 63
  • 10-bit tags : 320 - 511, 576 - 767

Note that all PFs and their associated VFs share the same tag space. This means that different PFs and VFs cannot have outstanding tags having the same tag values.

In the TLP bypass mode, there is no restriction on the tag allocation since the P-Tile PCIe Hard IP does not do any tag management. Hence, 10-bit tags can be used without any restriction across all the cores.

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