P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.1.2.2. Second-Level Debug Tools

Use the following debug tools for second-level debug of any issue observed on the PCI Express link when using P-Tile:

Using the Configuration Output Interface

Using the Error Interface

  • Refer to the section Error Interface for details on this interface and the address map.

Using the Configuration Intercept Interface

Using the TX/RX Flow Control Interfaces

Using the Hard IP Reconfiguration Interface

Using the PHY Reconfiguration Interface

Did you find the information on this page useful?

Characters remaining:

Feedback Message