4.6.1. Legacy Interrupts
Legacy interrupts mimic the original PCI level-sensitive interrupts using virtual wire messages. The P-tile IP for PCIe signals legacy interrupts on the PCIe link using Message TLPs. The term INTx refers collectively to the four legacy interrupts, INTA#,INTB#, INTC# and INTD#. The P-tile IP for PCIe asserts app_int_i to cause an Assert_INTx Message TLP to be generated and sent upstream. A deassertion of app_int_i, i.e a transition of this signal from high to low, causes a Deassert_INTx Message TLP to be generated and sent upstream. To use legacy interrupts, you must clear the Interrupt Disable bit, which is bit 10 of the Command Register in the configuration header. Then, you must turn off the MSI Enable bit.
|Signal Name||Direction||Description||Clock Domain||EP/RP/BP|
|I||When asserted, these signals indicate an assertion of an INTx message is requested. A transition from high to low indicates a deassertion of the INTx message is requested. This bus is for EP only. Each bit is associated with a corresponding physical function. These signals must be asserted for at least 8 cycles.||coreclkout_hip||EP|
|int_status_o||O||This signal drives legacy interrupts to the Application Layer in Root Port mode. The source of the interrupt will be logged in the Root Port Interrupt Status registers in the Port Configuration and Status registers.||coreclkout_hip||RP|
app_int_i is asserted for at least eight clock cycles to cause an Assert_INTx Message TLP to be generated and sent upstream for physical function 0. For a multi-functions implementation, app_int_i is for physical function 0, app_int_i is for physical function 1 and so on. Deasserting an app_int_i signal by driving it from high to low causes a Deassert_INTx Message TLP to be generated and sent upstream.
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