- Four PCIe* cores (one x16 core, one x8 core and two x4 cores)
- Embedded Multi-die Interconnect Bridge (EMIB)
- Soft logic blocks in the FPGA fabric to implement functions such as VirtIO, etc.
The four cores in the PCIe Hard IP can be configured to support the following topologies:
|Configuration Mode||Native IP Mode||Endpoint (EP) / Root Port (RP) / TLP Bypass (BP)||Active Cores|
|Configuration Mode 0||Gen3x16 or Gen4x16||EP/RP/BP||x16|
|Configuration Mode 1||Gen3x8/Gen3x8 or Gen4x8/Gen4x8||EP/BP||x16, x8|
|Configuration Mode 2||Gen3x4/Gen3x4/Gen3x4/Gen3x4 or Gen4x4/Gen4x4/Gen4x4/Gen4x4||RP/BP||x16, x8, x4_0, x4_1|
In Configuration Mode 0, only the x16 core is active, and it operates in x16 mode (in either Gen3 or Gen4).
In Configuration Mode 2, all four cores (x16, x8, x4_0, x4_1) are active, and they operate as four Gen3 x4 cores or four Gen4 x4 cores.
Each of the cores has its own Avalon® -ST interface to the user logic. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the configuration modes. For more details, refer to the Overview section of the Interfaces chapter.
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