When the TLP Bypass feature is enabled, the P-Tile Avalon® -ST IP does not process received TLPs internally but outputs them to the user application. This allows the application to implement a custom Transaction Layer.
Note that in TLP Bypass mode, the PCIe Hard IP does not generate/check the ECRC and will not remove it if the received TLP has the ECRC.
The P-tile Avalon® -ST IP in TLP Bypass mode still includes some of the PCIe configuration space registers related to link operation (refer to the Configuration Space Registers chapter for the list of registers).
In TLP bypass mode, P-Tile supports the autonomous Hard IP feature. It responds to configuration accesses before the FPGA fabric enters user mode with Completions with a CRS code.
However, in TLP bypass mode, CvP init and update are not supported.
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