P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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4.3. Serial Data Interface

P-Tile natively supports 4, 8, or 16 PCIe lanes. Each lane includes a TX differential pair and an RX differential pair. Data is striped across all available lanes. Refer to Variables Used in the Bus Indices for more details on bus indices.

Table 49.  Serial Data Interface
Signal Name Direction Description
tx_p_out[<b>-1:0], tx_n_out[<b>-1:0] O Transmit serial data outputs using the High Speed Differential I/O standard.
rx_p_in[<b>-1:0], rx_n_in[<b>-1:0] I Receive serial data inputs using the High Speed Differential I/O standard.

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