P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: hny1561091203039
Ixiasoft
Visible to Intel only — GUID: hny1561091203039
Ixiasoft
3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035 )
This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.
Bit Location | Description | Access Type | Default Value |
---|---|---|---|
31:0 | BAR Offset | RO | Settable through Platform Designer |