P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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Document Table of Contents

F.2.1. P-tile Dual-Endpoint System Configurations

The following table summarizes the dual-endpoint system configurations supported by P-tile:

Table 153.  Supported Dual-Endpoint System Configurations
Configuration Types REFCLK Source REFCLK Availability Port Connectivity
REFCLK0 REFCLK1 REFCLK0 REFCLK1 Port0 Port1
A Free-running 100MHz clock source 1 Free-running 100MHz clock source 2 During initial FPGA configuration During initial FPGA configuration Local SOC Host SOC
B Free-running 100MHz clock source 1 Free-running 100MHz clock source 2 During initial FPGA configuration During initial FPGA configuration Host SOC Local SOC
C Free-running 100MHz clock source 1 Free-running 100MHz clock source 1 During initial FPGA configuration During initial FPGA configuration Local SOC Host SOC
D Free-running 100MHz clock source 1 PCH During initial FPGA configuration May not be active during initial FPGA configuration Local SOC Host SOC

Supported System Configuration Type A: P-tile Port 0 and Port 1 with separate free-running clock sources. Both clocks are available during initial FPGA configuration. Port 0 is connected to a local SOC, Port 1 is connected to the Host.

Supported System Configuration Type B: P-tile Port 0 and Port 1 with separate free-running clock sources. Both clocks are available during initial FPGA configuration. Port 0 is connected to the Host, Port 1 is connected to a local SOC.

Supported System Configuration Type C: Host port is connected via SRIS or SRNS. P-tile port 0 and 1 use a common free-running local reference clock available during initial FPGA configuration. This is the preferred solution to support independent endpoint system integration.

Supported System Configuration Type D: Port 0 and Port 1 with separate refclk sources. Port 0 is connected to a local SOC, Port 1 is connected to the Host. The Local SOC/Port 0 refclk clock is an always available free-running clock source. The Host refclk is driven from PCH, which may lose power while the FPGA has power, and/or may not be powered up during the FPGA initial configuration.

You must disable the IP Parameter Editor option Port 1 REFCLK init active for Type D configuration.

Unsupported System Configuration Type E: Port 0 and Port 1 with separate refclk sources. Port 0 is connected to the Host, Port 1 is connected to a local SOC. The Local SOC/Port 1 refclk clock is an always available free-running clock source. The Host refclk is driven from PCH, which may lose power while the FPGA has power, and/or may not be powered up during the FPGA initial configuration. P-tile will NOT support this configuration.

Note that the PERST# inputs that come via GPIOs (like i_gpio_perst0_n and i_gpio_perst1_n) need to go through some debounce logic (to be implemented in user logic) before connecting to the P-tile Hard IP as shown in the figure below.

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