P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34)

This register reports the status of the internally checked errors that are uncorrectable. When these specific errors are enabled by the Uncorrectable Internal Error Mask register, they are forwarded as Uncorrectable Internal Errors.

Note: This register is for debug only. Only use this register to observe behavior, not to drive logic custom logic.
Table 146.  Uncorrectable Internal Error Status Register
Bits Register Description Default Value Access
[31:13] Reserved 0x0 RO
[12] Debug Bus Interface (DBI) access error status from Config RAM block. 0x0 RW1CS
[11] Uncorrectable ECC error from Config RAM block. 0x0 RW1C
[10:9] Reserved 0x0 RO
[8] RX Transaction Layer parity error reported by the IP core. 0x0 RW1CS
[7] TX Transaction Layer parity error reported by the IP core. 0x0 RW1CS
[6]

Uncorrectable Internal Error reported by the FPGA.

0x0 RW1CS
[5] cvp_config_error_latched: Configuration error detected in CvP mode is reported as an uncorrectable error. Set whenever ssm_cvp_config_error of the SSM Scratch CvP Status register bit[1] rises in CvP mode. This bit is only available for Port 0 ( PCIe* Gen4 x16), but not for the other Ports. 0x0 RW1CS
[4:0] Reserved 0x0 RO
Note: The access code RW1CS represents Read Write 1 to Clear Sticky.

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