P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 3/28/2022
Public

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4.2.1. Interface Clock Signals

Table 46.  Interface Clock Signals
Name I/O Description EP/RP/BP Clock Frequency
coreclkout_hip O

This clock drives the Application Layer.

The frequency depends on the data rate and the number of lanes being used.

EP/RP/BP

Native Gen3: 250 MHz

Native Gen4: 175 MHz / 200 MHz / 225 MHz / 350 MHz / 400 MHz / 450 MHz ( Intel® Stratix® 10 DX)

Native Gen4: 175 MHz / 200 MHz / 225 MHz / 250 MHz / 350 MHz / 400 MHz / 450 MHz / 500 MHz ( Intel® Agilex™ )

refclk[1:0] I

These are the input reference clocks for the IP core. These clocks must be free-running.

For more details on how to connect these clocks, refer to the section Clock Sharing in Bifurcation Modes.

EP/RP/BP 100 MHz ± 300 ppm
p<n>_hip_reconfig_clk I Clock for the hip_reconfig interface. This is an Avalon® -MM interface. It is an optional interface that is enabled when the Enable HIP dynamic reconfiguration of PCIe read-only registers option in the PCIe Configuration, Debug and Extension Options tab is enabled. EP/RP/BP

50 MHz - 125 MHz (range)

100 MHz (recommended)

xcvr_reconfig_clk I Clock for the PHY reconfiguration interface. This is an Avalon® -MM interface. This optional interface is enabled when you turn on the Enable PHY reconfiguration option in the Top-Level Settings tab. This interface is shared among all the cores. EP/RP/BP

50 MHz - 125 MHz (range)

100 MHz (recommended)

p<n>_cpl_timeout_avmm_clk I Avalon® -MM clock for Completion timeout interface. This interface is optional, and is enabled when the Enable Completion Timeout Interface option in the PCIe Avalon Settings tab is enabled. EP/RP/BP

50 MHz - 125 MHz (range)

100 MHz (recommended)

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