Stratix® 10 devices use a parallel, sector-based architecture that
distributes the core fabric logic across multiple sectors. Device configuration proceeds in
parallel with each Local Sector Manager (LSM) configuring its own sector. Consequently,
Stratix® 10 registers and core logic are not released from reset
at exactly the same time, as has always been the case in previous families.
The continual increases
in clock frequency, device size, and design complexity
now necessitate a
well-thought out reset
that considers the possible effects of slight differences in the release
from reset. This reset
strategy must hold the device in reset until all registers and core logic are in user mode.
Intel strongly recommends that you use the nINIT_DONE output of the Reset Release
Stratix® 10 FPGA IP as one of the initial inputs to your reset
Using the Reset Release Intel Stratix 10 FPGA IP
The Reset Release
Stratix® 10 FPGA IP holds
a control circuit in reset until the device has fully entered user mode. The
Stratix® 10 device
to signal that the device is fully in user mode. The Reset Release
Stratix® 10 FPGA IP generates an inverted version of the internal INIT_DONE signal, nINIT_DONE
for use in your
nINIT_DONE is high until the entire device enters user
mode. After nINIT_DONE asserts (low), all
logic is in user mode
and operates normally. You can use the nINIT_DONE signal in one of the following ways:
To gate an external or internal reset.
To gate the reset input to the
To gate the write enable of design blocks such as embedded memory
blocks, state machine, and shift registers.
To synchronously drive register reset input ports in your design.
Attention: When you instantiate Reset
Stratix® 10 FPGA IP in your design, the
selects one Local Sector Manager (LSM) to output the nINIT_DONE signal. Do not instantiate multiple instances of this IP. If multiple
instances exist, a different LSM
instance, resulting in some skew between the nINIT_DONE
Instantiating the Reset Release IP In Your Design
The Reset Release IP is available in the IP Catalog in the
Basic Functions > Configuration and Programming category. This IP has no parameters.
Complete the following steps to instantiate the Reset
Release IP in your design.
In the IP Catalog, type reset release in the search window to
find the Reset Release
Stratix® 10 FPGA IP.
Figure 1. Locate Reset Release
Stratix® 10FPGA IP in IP
Double click the Reset Release
Stratix® 10 FPGA
IP to add the Reset Release IP to your design.
In the New IP Variant
dialog box, browse to your IP directory and specify a file name for the Reset
Release IP. Then click Create.
The Reset Release IP is now included in your
Assigning INIT_DONE To an SDM_IO Pin
If you choose to route INIT_DONE to an external pin, you must assign
INIT_DONE to an SDM_IO pin.
Complete the following steps to make this
Quartus® Prime Assignments menu, select Device > Device and Pin Options > Configuration Pin, turn on the Use INIT_DONE output.
In the drop-down list, select any SDM_IO pin that is available.
Figure 2. Assigning INIT_DONE to SDM_IO Pin
Note: The Reset
generates the nINIT_DONE internal signal whether or not you
choose to assign INIT_DONE to an SDM_IO pin.
Gating an External Reset
If your design is held in reset using an externally sourced reset
signal, you should gate this external reset.
You have two options for gating an external reset:
Use the INIT_DONE output signal to gate
Use nINIT_DONE from the Reset Release
IP to gate the external reset source after this reset enters the device.
You can also feed the external INIT_DONE signal directly
back into the FPGA through an external pin-to-pin connection in place of the Reset Release IP.
Note that any external signal may not be immediately effective in the fabric while the FPGA is
initializing. Furthermore, I/O is frozen as logic 1 until activated. Consequently, Intel recommends using an active high external reset.
Gating the PLL Reset Signal
In older FPGA device families, designs frequently used the PLL lock signal to
hold the custom FPGA logic in reset until the PLL locked. In
Stratix® 10 devices the lock time of PLLs can be less than the initialization time. In
some cases the PLL may lock before the
Consequently, if you use the locked output of the PLL to control resets in
Stratix® 10 devices, you should gate the
reset input with nINIT_DONE as shown the
Figure 3. Using nINIT_DONE to Gate the PLL_Reset Signal
Another alternative if you are using PLL_Lock in your reset sequence is to gate the PLL_Lock output with the nINIT_DONE signal,
Guidance When Using Partial Reconfiguration (PR)
provides reset logic that ensures that the static region of the device and
the PR personas do not interact during PR.
The Reset Release IP is only necessary to manage reset for full FPGA core
configuration and subsequent full FPGA core configurations. The Reset Release IP is not
necessary to prevent interaction between the static and PR personas during the PR process. For
more information about PR refer to the
Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.
Each Local Sector Manager (LSM) configures its own sector. A sector comprises
multiple logic array block (LAB) rows. A logical function can span multiple rows and multiple
During configuration global configuration control signals hold the core fabric in a frozen
state to prevent electrical contention. The LSMs work in parallel to asynchronously unfreeze
the sectors. Within a sector the LSM unfreezes LAB rows and registers in the LABs
sequentially. The LSMs work to unfreeze the fabric in parallel across all sectors without
synchronization. Consequently, logic in different sectors or in the same sector but in
different rows could begin to operate while other logic is still frozen. The
INIT_DONE signal asserts when all the LSMs have entered user mode.
Figure 4. Releasing LAB Rows and Registers in the LABs Sequentially and Asynchronously Across
The following topics provide more detail about device configuration and
initialization, and possible consequences if you do not use the Reset Release IP to hold the
Stratix® 10 device in reset until entire fabric enters user mode.
Intel Stratix 10 Device Initialization
The following steps summarize
Stratix® 10 device initialization:
An external host drives a configuration request to the Secure Device
Manager (SDM) by driving nCONFIG high. The SDM exits the
IDLE state and signals the beginning of configuration by driving nSTATUS high and driving configuration data.
The SDM asserts CONF_DONE indicating
Stratix® 10 device has successfully received all the
The SDM uses the configuration logic to start non-gated clocks in the
registers begin shifting data.
Consequently, the initial conditions of
registers can be random. Use the Disable Register Power-up
Initialization setting in the
Quartus® PrimeConfiguration dialog box to disable
register initialization during power-on as explained
The SDM uses the configuration logic to enable and initialize user
registers in the LABs, DSP, and embedded memory blocks.
The SDM drives INIT_DONE to indicate that
the device has fully entered user mode. The Reset Release IP asserts nINIT_DONE. Intel recommends that you
use nINIT_DONE to gate your reset logic.
The FPGA is now in user mode and ready for operation.
For more detailed information about the configuration flow, refer to the
Stratix® 10 Configuration User
Preventing Register Initialization During Power-On
If not held in reset, both ALM and
registers may lose their initial state if they initialize before their
You can prevent registers from
initializing during power-on by enabling an option in the
Quartus® Prime software. Complete the following steps to turn on this option:
On the Assignments menu select Device > Device and Pin Options > Configuration.
In the Configuration dialog box, turn on Disable
Register Power-up Initialization.
Figure 5. Disabling Register Initialization During Power-On
Intel also recommends that
you not use initial conditions in your register transfer level (RTL)
Embedded Memory Block Initial Conditions
Initialized content of embedded memory blocks is stable during
configuration. However, designs that contain logic to modify embedded memory can result in
spurious writes. Spurious writes can occur if you fail to gate the write enable with an
Protecting State Machine Logic
To guarantee correct operation of state machines, your reset logic must hold the FPGA
fabric in reset until the entire fabric enters user mode.
The following example shows how an inadequate reset strategy might result in
an illegal state in a one-hot state machine.
In this example, the
design does not reset any of the state machine registers. The state machine design
entering an initial state. Without an adequate reset,
state machine begins operating when part of the device is active. Nearby logic included in the
state machine remains frozen, before
Register B in the active section is operational and takes on the value of
Register A in the next clock cycle. Register A is still in the freeze register state and does
not respond to the clock edge. Register A remains in the current state.
Figure 7. Advance One Clock Cycle, Device Completely In User Mode - INIT_DONE =
The entire fabric is now in user mode. The state machine enters an illegal or
unknown state with two ones in a one-hot state machine. To prevent this illegal state, use the
Reset Release IP to hold the circuit in reset until INIT_DONE
asserts indicating that the entire fabric has entered user mode.
Document Revision History for AN 891: Reset Release Intel Stratix 10 FPGA IP