New and Updated Design Assistant Rules for 25.3 Release

Newly Added Design Assistant Rules

No newly added rules for 25.3 release.

Updated Design Assistant Rules

1-Bit Asynchronous Transfer Not Synchronized
1-Bit Asynchronous Transfer with Insufficient Constraints
CE-Type CDC Transfer with Insufficient Constraints
MUX-type CDC Transfer with Insufficient Constraints
CDC Bus Constructed with Multi-bit Synchronizer Chains of Different Lengths
CDC Bus Constructed with Unsynchronized Registers
CDC Bus Constructed with Multi-bit Synchronizer Chains with Insufficient Constraints
CDC Bus Constructed with Multi-bit Synchronizer Chains
Combinational Logic Before Synchronizer Chain
Reconvergence of Multiple Asynchronous Reset Synchronizers in Different Reset Domains
Reconvergence of Multiple Asynchronous Reset Synchronizers in a Common Reset Domain
Multiple Asynchronous Reset Synchronizers in the Same Clock Domain
Asynchronous Reset Is Not Synchronized
Asynchronous Reset is Insufficiently Synchronized
Asynchronous Reset with Insufficient Constraints

BBD-60000: Partial Reconfiguration or Reserved Core Input/Output Ports not Directly Registered
BBD-60001: Partial Reconfiguration or Reserved Core Input Port(s) does not Drive a Register
BBD-60002: Partial Reconfiguration or Reserved Core Output Port(s) is Driven by a Constant
CDC-50001: 1-Bit Asynchronous Transfer Not Synchronized
CDC-50002: 1-Bit Asynchronous Transfer with Insufficient Constraints
CDC-50003: CE-Type CDC Transfer with Insufficient Constraints
CDC-50004: MUX-type CDC Transfer with Insufficient Constraints
CDC-50005: CDC Bus Constructed with Multi-bit Synchronizer Chains of Different Lengths
CDC-50006: CDC Bus Constructed with Unsynchronized Registers
CDC-50007: CDC Bus Constructed with Multi-bit Synchronizer Chains with Insufficient Constraints
CDC-50008: CDC Bus Constructed with Multi-bit Synchronizer Chains
CDC-50011: Combinational Logic Before Synchronizer Chain
CDC-50012: Multiple Clock Domains Driving a Synchronizer Chain
CDC-50101: Intra-Clock False Path Synchronizer
CDC-50102: Synchronizer after CDC Topology with Control Signal
CDC-50103: Unsynchronized Intra-Clock Forced Synchronizer
CLK-30026: Missing Clock Assignment
CLK-30027: Multiple Clock Assignments Found
CLK-30028: Invalid Generated Clock
CLK-30029: Invalid Clock Assignments
CLK-30030: PLL Setting Violation
CLK-30031: Input Delay Assigned to Clock
CLK-30032: Improper Clock Targets
CLK-30033: Invalid Clock Group Assignment
CLK-30034: Clock Pairs Missing Logically Exclusive Clock Group Assignment
CLK-30035: Clock Pairs Missing Physically Exclusive Clock Group Assignment
CLK-30042: Incorrect Clock Group Type
CUS-20000: Hello world rule
CUS-20001: Another hello world rule template sharing check operation parameters
CUS-30001: Fake custom rule
FLP-10000: Physical RAM with Utilization Below Threshold
FLP-10100: Large Multipliers are Decomposed
FLP-10500: Non Driving Top Level Inputs Found
FLP-10501: Top-Level Ports Without Pin Location Assignment
FLP-40001: Congested Placement Region
FLP-40002: Very Small Routing Regions
FLP-40003: Narrow Region
FLP-40005: Congested Routing Region
FLP-40006: Pipelining Registers That Might Be Recoverable
IPC-40021: Undriven Reference Clock port of protocol IP
IPC-40022: Reference Clock input of protocol IP not driven by top level clock ports
IPC-40023: Reference clock frequency mismatch
IPC-40024: Undriven System Clock port of protocol IP
IPC-40025: System Clock ports of protocol IP not driven by System Clock IP
IPC-40026: System clock frequency mismatch
IPC-40027: Undriven Control Unit Clock port of protocol IP
IPC-40028: The Control Unit Clock port of protocol IP is not driven by GTS Reset Sequencer IP
IPC-40029: An individual bit of Control Unit clock port of Reset Sequencer IP can drive up to a cumulative 4 channels of Protocol IP.
IPC-40030: Reset Request and Grant connectivity checks for protocol IPs
IPC-40031: The individual Request and Grant bus bits of GTS Reset Sequencer IP to handle the same bits of request and grant ports protocol IP
IPC-40032: The lock input of the Protocol IP needs to be driven by the lock output of the System Clock IPs
IPC-40034: A single Reference clock port can drive up to 12 channels
IPC-40035: Reset Sequencer needed for Transceiver IPs
IPC-40036: Single Reset Sequencer for every IP on each shoreline
IPC-40037: Exclusive usage of the System Clock by PCIE IP
IPC-40038: Individual bit of Control Unit clock of Reset Sequencer IP can drive only a single instance of Ethernet or PCIE IP.
IPC-40039: One or more input or output ports of GTS Reset Sequencer IP not connected to Protocol IPs
IPC-40041: Transceiver IPs used in design with a device without any transceiver
LNT-30010: Nets Driving both Reset and Clock Enable Signals
LNT-30011: Design Contains Combinational Loops
LNT-30017: Register Output Driving Its Own Asynchronous Control Signal Directly or Through Combinational Logic
LNT-30020: Same Signal Source Drives Synchronous and Asynchronous Ports of the Same Register
LNT-30021: Same Signal Source Drives More Than One Asynchronous Port of a Register
LNT-30022: Same Signal Source Drives Clock Port and Another Port of a Register
LNT-30023: Reset Nets with Polarity Conflict
LNT-30024: LUT With More Than 1 Input Driving Clock Pins
LNT-30025: LUT With More Than 1 Input Driving Asynchronous Pins
LNT-30026: LUT With More Than 1 Input Driving Primary Device Output Ports
LNT-50006: DSP Control Signal Registers Reset Mode Mismatch
LNT-50007: Unregistered DSP Chain Connections
PDI-20100: Platform Designer Interconnect Timing Violation
PDI-20101: Platform Designer Interconnect Burst Adapter Timing Violation
PRJ-10000: INI Variables Used During Compile
PRJ-10001: INI Variables Set and Not Used During Compile
RDC-50001: Reconvergence of Multiple Asynchronous Reset Synchronizers in Different Reset Domains
RDC-50002: Reconvergence of Multiple Asynchronous Reset Synchronizers in a Common Reset Domain
RDC-50003: Multiple Asynchronous Reset Synchronizers in the Same Clock Domain
RES-10201: Power Up Don't Care Setting May Prevent Retiming
RES-10202: Register Power-Up Settings Conflict with Device Settings
RES-10203: Registers with Initial Conditions
RES-10204: Reset Release Instance Count Check
RES-30132: Registers May Not Be Properly Reset
RES-30133: Embedded Memory Blocks with Initialized Content That Might be Modified Before the FPGA Enters User Mode
RES-30134: Registers Not Reachable from Reset Release IP
RES-50001: Asynchronous Reset Is Not Synchronized
RES-50002: Asynchronous Reset is Insufficiently Synchronized
RES-50003: Asynchronous Reset with Insufficient Constraints
RES-50004: Multiple Asynchronous Resets within Reset Synchronizer Chain
RES-50005: RAM Control Signals Driven by Flip-Flops with Asynchronous Clears
RES-50010: Reset Synchronizer Chains with Constant Output
RES-50101: Intra-Clock False Path Reset Synchronizer
TMC-10107: Maximum Fan-out for Signal
TMC-10115: High Fan-out Signal
TMC-20001: Timing Paths with Hold Slack Exceeding Threshold
TMC-20002: Timing Paths with Removal Slack Exceeding Threshold
TMC-20003: Unconstrained IO path
TMC-20004: Timing Paths with Setup Slack Exceeding Threshold
TMC-20005: Timing Paths with Recovery Slack Exceeding Threshold
TMC-20006: Unregistered Partition Inputs
TMC-20007: Unregistered Paths Between Partitions
TMC-20010: Logic Level Depth
TMC-20011: Missing Input Delay Constraint
TMC-20012: Missing Output Delay Constraint
TMC-20013: Partial Input Delay
TMC-20014: Partial Output Delay
TMC-20015: Inconsistent Min-Max Delay
TMC-20016: Invalid Reference Pin
TMC-20017: Loops Detected
TMC-20018: Unsupported Latches Detected
TMC-20019: Partial Multicycle Assignment
TMC-20020: Invalid Multicycle Assignment
TMC-20021: Partial Min-Max Delay Assignment
TMC-20022: I/O Delay Assignment Missing Parameters
TMC-20023: Invalid Set Net Delay Assignment
TMC-20024: Synchronous Data Delay Assignment
TMC-20025: Ignored or Overridden Constraints
TMC-20026: Empty Collection Due To Unmatched Filter
TMC-20027: Collection Filter Matching Multiple Types
TMC-20050: RAM Control Signals Driven by LUTs or ALMs instead of DFFs
TMC-20051: RAM Control Signals Driven by High Fan-Out Net
TMC-20052: Paths with Post Synthesis Inferred Latches
TMC-20053: DSP Inputs Driven by High Fan-Out Net
TMC-20100: Latch Loops Detected
TMC-20200: Paths Failing Setup Analysis with Impossible Requirements
TMC-20201: Paths Failing Setup Analysis with High Clock Skew
TMC-20202: Paths Failing Setup Analysis with High Logic Delay
TMC-20203: Paths Failing Setup Analysis with High Fabric Interconnect Delay
TMC-20204: Endpoints of Paths Failing Setup Analysis with Retiming Restrictions
TMC-20205: Endpoints of Paths Failing Setup Analysis with Explicit Power-Up States that Restrict Retiming
TMC-20206: DSP Blocks with Unregistered Outputs that are the Source of Paths Failing Setup Analysis
TMC-20207: DSP Blocks with Unregistered Inputs that are the Destination of Paths Failing Setup Analysis
TMC-20208: RAM Blocks with Unregistered Outputs that are the Source of Paths Failing Setup Analysis
TMC-20209: Paths Failing Setup Analysis with High Routing Delay due to Congestion
TMC-20210: Paths Failing Setup Analysis with High Routing Delay Added for Hold
TMC-20212: Paths Failing Setup Analysis with Global Routing in Data Path
TMC-20213: Paths Failing Setup Analysis with Locally Routed Clock
TMC-20214: Buses with Incoming Paths Failing Setup Analysis with Multiple Sequential Adder Chains
TMC-20215: Buses with Incoming Paths Failing Setup Analysis with Multipliers Implemented in Logic
TMC-20216: Paths Failing Setup Analysis with Inferred-RAM Shift Register Endpoints
TMC-20217: Paths Failing Setup Analysis with Clock-As-Data
TMC-20219: DSP Blocks with Restricted Fmax below Required Fmax
TMC-20220: RAM Blocks with Restricted Fmax below Required Fmax
TMC-20221: Nodes Failing Minimum Pulse Width Due to Clock Pulse Collapse
TMC-20250: Paths Failing Setup Analysis within Platform Designer Interconnect
TMC-20251: Paths Failing Setup Analysis within Platform Designer Interconnect Burst Adapter
TMC-20312: Paths Failing Hold Analysis with Global Routing in Data Path
TMC-20313: Paths Failing Hold Analysis with Locally Routed Clock
TMC-20500: Hierarchical Tree Duplication was Shallower than Possible
TMC-20501: Hierarchical Tree Duplication was Shallower than Requested
TMC-20550: Automatically Selected Duplication Candidate Rejected for Placement Constraint
TMC-20551: Automatically Selected Duplication Candidate Likely Requires More Duplication
TMC-20552: User Selected Duplication Candidate was Rejected
TMC-20601: Registers with High Immediate Fan-Out Tension
TMC-20602: Registers with High Timing Path Endpoint Tension
TMC-20603: Registers with High Immediate Fan-Out Span
TMC-20604: Registers with High Timing Path Endpoint Span
TMC-20605: Register Wirelut FO Check
TMC-20712: Paths Failing Recovery Analysis with Global Routing in Data Path
TMC-20713: Paths Failing Recovery Analysis with Locally Routed Clock
TMC-20812: Paths Failing Removal Analysis with Global Routing in Data Path
TMC-20813: Paths Failing Removal Analysis with Locally Routed Clock
TMC-30041: Constraint with Invalid Clock Reference

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