IPC-40023: Reference clock frequency mismatch

Description

Reference clock ports of protocol IP must be driven, if present. These ports can be driven only by top level clock ports.

Furthermore, reference clock frequencies of all reference clock inputs, be System clock or Protocol IPs, driven by the same top level clock port must match.

Figure 1. Reference clock frequencies of Protocl IPs and System Clock IPs driven by same top level top should match.

Recommendation

Either correct the connection to ensure that only system clock inputs of protocol/system clock IPs of matching frequencies are connected to a top level clock port or regenerate the system clock or protocol IPs with the right system clock frequency parameters.

Severity

Critical

Tags

Tag Description
system Design rule checks which validate full-system design.

Device Family

  • Agilex®