BBD-60000: Partial Reconfiguration or Reserved Core Input/Output Ports not Directly Registered
Description
Violations of this rule identify the Partial Reconfiguration (or Reserved Core) partition input/output boundary ports that are not directly connected to FF/RAM/DSP.
Connecting the Partial Reconfiguration (or Reserved Core) partition input/output ports to FF/RAM/DSP helps with timing closure.
Note: This rule will only check Partial Reconfiguration (or Reserved Core) designs.
Recommendation
In the HDL design files, define registers at the input and output boundary ports of Partial Reconfiguration (or Reserved Core) partitions.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| partial-reconfiguration | Design rule checks which check Partial Reconfiguration designs. |
Device Family
- Arria® 10
- Stratix® 10
- Agilex®
- Agilex®
- Agilex®