LNT-30025: LUT With More Than 1 Input Driving Asynchronous Pins


Violations of this rule identify lookup tables that combine more than one input signal and drive into asynchronous control pins of registers. Any time a lookup table has multiple inputs, there is a risk of signal transitions arriving at those inputs at different times and creating glitches at the LUT output. These relative delays may differ between compiles as the optimization solution changes.

Without careful consideration and timing constraints, glitches on asynchronous ports can result in spurious rising or falling transitions and cause functional issues in the destination registers.


If the violating LUT cannot be removed or its output cannot be registered, ensure that it is properly timing constrained to avoid glitches and waive its violation.




Tag Description
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.

Device Family

  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®
  • Intel®Stratix® 10
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX